TY - GEN
T1 - A strong arbiter PUF using resistive RAM within 1T-1R memory architecture
AU - Govindaraj, Rekha
AU - Ghosh, Swaroop
N1 - Funding Information:
This paper is based on work supported by Semiconductor Research Corporation (#2442.001) and NSF CNS 1441757.
PY - 2016/11/22
Y1 - 2016/11/22
N2 - Physically Unclonable Function (PUF) is cost effective and reliable security primitives widely used in authentication and in-place secret key generation. With growing research in the area of non-CMOS technologies for memories and circuits, it is important to understand their implications on the design of security primitives. Resistive Random Accessible Memory (RRAM) offers easy integration with CMOS due to minimal changes in the process technology. RRAM also demonstrates resistance variability characteristics due to inherent defects in the conducting filament formed inside the metal oxide layer. RRAM based PUF designs exploit either the probabilistic switching of RRAM or the resistance variability during forming, SET and RESET processes. Memory PUFs using RRAM are typically weak PUFs due to fewer number of Challenge Response Pairs (CRPs). We propose strong arbiter PUF based on 1T-1R bit cell which is obtained from conventional RRAM memory array with minimally invasive changes. Conventional voltage sense amplifier is employed to generate the response. The PUF is simulated using 65nm predictive technology models for CMOS and Verilog-A model for a hafnium oxide based RRAM. The proposed PUF architecture is evaluated for uniqueness, uniformity and reliability and by running NIST benchmarks. It demonstrates mean intra-die Hamming Distance (HD) of 0.13% and inter-die HD of 51.3%, and, passes the NIST tests.
AB - Physically Unclonable Function (PUF) is cost effective and reliable security primitives widely used in authentication and in-place secret key generation. With growing research in the area of non-CMOS technologies for memories and circuits, it is important to understand their implications on the design of security primitives. Resistive Random Accessible Memory (RRAM) offers easy integration with CMOS due to minimal changes in the process technology. RRAM also demonstrates resistance variability characteristics due to inherent defects in the conducting filament formed inside the metal oxide layer. RRAM based PUF designs exploit either the probabilistic switching of RRAM or the resistance variability during forming, SET and RESET processes. Memory PUFs using RRAM are typically weak PUFs due to fewer number of Challenge Response Pairs (CRPs). We propose strong arbiter PUF based on 1T-1R bit cell which is obtained from conventional RRAM memory array with minimally invasive changes. Conventional voltage sense amplifier is employed to generate the response. The PUF is simulated using 65nm predictive technology models for CMOS and Verilog-A model for a hafnium oxide based RRAM. The proposed PUF architecture is evaluated for uniqueness, uniformity and reliability and by running NIST benchmarks. It demonstrates mean intra-die Hamming Distance (HD) of 0.13% and inter-die HD of 51.3%, and, passes the NIST tests.
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U2 - 10.1109/ICCD.2016.7753272
DO - 10.1109/ICCD.2016.7753272
M3 - Conference contribution
AN - SCOPUS:85006724627
T3 - Proceedings of the 34th IEEE International Conference on Computer Design, ICCD 2016
SP - 141
EP - 148
BT - Proceedings of the 34th IEEE International Conference on Computer Design, ICCD 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 34th IEEE International Conference on Computer Design, ICCD 2016
Y2 - 2 October 2016 through 5 October 2016
ER -