A study on performance and power efficiency of dense non-volatile caches in multi-core systems

Amin Jadidi, Mohammad Arjomand, Mahmut Kandemir, Chita Das

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

This paper presents a novel cache design based on Multi-Level Cell Spin-Transfer Torque RAM (MLC STT-RAM). Our design exploits the asymmetric nature of the MLC STT-RAM to build cache lines featuring heterogeneous performances, that is, half of the cache lines are read-friendly, while the other half are write-friendly -This asymmetry in read/write latencies are then used by a migration policy in order to overcome the high latency of the baseline MLC cache. Furthermore, in order to enhance the device lifetime, we propose to dynamically deactivate ways of a set in underutilized sets to convert MLC to Single-Level Cell (SLC) mode. Our experiments show that our design gives an average improvement of 12% in system performance and 26% in last-level cache (L3) access energy for various workloads.

Original languageEnglish (US)
Title of host publicationSIGMETRICS 2017 Abstracts - Proceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems
PublisherAssociation for Computing Machinery, Inc
Pages27-28
Number of pages2
ISBN (Electronic)9781450350327
DOIs
StatePublished - Jun 5 2017
Event2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, SIGMETRICS 2017 - Urbana-Champaign, United States
Duration: Jun 5 2017Jun 9 2017

Publication series

NameSIGMETRICS 2017 Abstracts - Proceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems

Other

Other2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, SIGMETRICS 2017
CountryUnited States
CityUrbana-Champaign
Period6/5/176/9/17

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Computer Networks and Communications
  • Computational Theory and Mathematics

Fingerprint Dive into the research topics of 'A study on performance and power efficiency of dense non-volatile caches in multi-core systems'. Together they form a unique fingerprint.

  • Cite this

    Jadidi, A., Arjomand, M., Kandemir, M., & Das, C. (2017). A study on performance and power efficiency of dense non-volatile caches in multi-core systems. In SIGMETRICS 2017 Abstracts - Proceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems (pp. 27-28). (SIGMETRICS 2017 Abstracts - Proceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems). Association for Computing Machinery, Inc. https://doi.org/10.1145/3078505.3078547