TY - JOUR
T1 - A Study on Performance and Power Efficiency of Dense Non-Volatile Caches in Multi-Core Systems
AU - Jadidi, Amin
AU - Arjomand, Mohammad
AU - Kandemir, Mahmut
AU - Das, Chita
N1 - Funding Information:
4 ACKNOWLEDGMENT This work is supported in part by NSF grants 1302557, 1213052, 1439021, 1302225, 1629129, 1526750, and 1629915, a grant from Intel.
PY - 2017/6/5
Y1 - 2017/6/5
N2 - This paper presents a novel cache design based on Multi-Level Cell Spin-Transfer Torque RAM (MLC STT-RAM).Our design exploits the asymmetric nature of the MLC STT-RAM to build cache lines featuring heterogeneous performances, that is, half of the cache lines are read-friendly,while the other half are write-friendly-this asymmetry in read/write latencies are then used by a migration policy in order to overcome the high latency of the baseline MLC cache. Furthermore, in order to enhance the device lifetime, we propose to dynamically deactivate ways of a set in underutilized sets to convert MLC to Single-Level Cell (SLC)mode.Our experiments show that our design gives an average improvement of 12% in system performance and 26% in last-level cache(L3) access energy for various workloads.
AB - This paper presents a novel cache design based on Multi-Level Cell Spin-Transfer Torque RAM (MLC STT-RAM).Our design exploits the asymmetric nature of the MLC STT-RAM to build cache lines featuring heterogeneous performances, that is, half of the cache lines are read-friendly,while the other half are write-friendly-this asymmetry in read/write latencies are then used by a migration policy in order to overcome the high latency of the baseline MLC cache. Furthermore, in order to enhance the device lifetime, we propose to dynamically deactivate ways of a set in underutilized sets to convert MLC to Single-Level Cell (SLC)mode.Our experiments show that our design gives an average improvement of 12% in system performance and 26% in last-level cache(L3) access energy for various workloads.
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U2 - 10.1145/3078505.3078547
DO - 10.1145/3078505.3078547
M3 - Article
AN - SCOPUS:85021826893
VL - 45
SP - 27
EP - 28
JO - Performance Evaluation Review
JF - Performance Evaluation Review
SN - 0163-5999
IS - 1
ER -