A switch cache design for MIN-based shared-memory multiprocessors

Mazin S. Yousif, Chita R. Das

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this work, we investigate the idea of incorporating caches into selected switching elements of a multistage interconnection network (MIN)-based multiprocessor. Along with the processor private caches, these switch caches form a two-level cache hierarchy. Selected switch caches within a particular stage of the MIN are connected by a coherence control bus, through which a write-invalidate cache coherence protocol maintains coherence of private and switch caches. The impact of the protocol on system performance is evaluated through a simulation-based performance study, which shows that it is feasible to build large shared-memory cache-coherent multiprocessor systems.

Original languageEnglish (US)
Title of host publicationParallel Processing
Subtitle of host publicationCONPAR 1994 - VAPP VI - 3rd Joint International Conference on Vector and Parallel Processing, Proceedings
EditorsBruno Buchberger, Jens Volkert
PublisherSpringer Verlag
Pages426-437
Number of pages12
ISBN (Print)9783540584308
DOIs
StatePublished - Jan 1 1994
Event3rd Joint International Conference on Vector and Parallel Processing, CONPAR 1994 - VAPP VI - Linz, Austria
Duration: Sep 6 1994Sep 8 1994

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume854 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Other

Other3rd Joint International Conference on Vector and Parallel Processing, CONPAR 1994 - VAPP VI
CountryAustria
CityLinz
Period9/6/949/8/94

All Science Journal Classification (ASJC) codes

  • Theoretical Computer Science
  • Computer Science(all)

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  • Cite this

    Yousif, M. S., & Das, C. R. (1994). A switch cache design for MIN-based shared-memory multiprocessors. In B. Buchberger, & J. Volkert (Eds.), Parallel Processing: CONPAR 1994 - VAPP VI - 3rd Joint International Conference on Vector and Parallel Processing, Proceedings (pp. 426-437). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 854 LNCS). Springer Verlag. https://doi.org/10.1007/3-540-58430-7_38