A synthesis algorithm for reconfigurable single-electron transistor arrays

Yung Chih Chen, Soumya Eachempati, Chun Yao Wang, Suman Datta, Yuan Xie, Vijaykrishnan Narayanan

Research output: Contribution to journalArticle

18 Scopus citations

Abstract

Reducing power consumption has become one of the primary challenges in chip design, and therefore significant efforts are being devoted to find holistic solutions on power reduction from the device level up to the system level. Among a plethora of low power devices that are being explored, single-electron transistors (SETs) at room temperature are particularly attractive. Although prior work has proposed a binary decision diagram-based reconfigurable logic architecture using SETs, it lacks an automatic synthesis algorithm for the architecture. Consequently, in this work, we develop a product-term-based approach that synthesizes a logic circuit by mapping all its product terms into the SET architecture. The experimental results show the effectiveness and efficiency of the proposed approach on a set of MCNC benchmarks.

Original languageEnglish (US)
Article number5
JournalACM Journal on Emerging Technologies in Computing Systems
Volume9
Issue number1
DOIs
StatePublished - Feb 1 2013

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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