A threshold switch augmented hybrid-FeFET (H-FeFET) with enhanced read distinguishability and reduced programming voltage for non-volatile memory applications

M. Jerry, A. Aziz, K. Ni, S. Datta, Sumeet Kumar Gupta, N. Shukla

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In this work, we demonstrate a novel Hybrid-FeFET (H-FeFET) that leverages the threshold switching characteristics of Ag/HfO2 to overcome the fundamental trade-off between memory window MW /read current ratio (Iread,1/Iread,0) , and program voltage (Vprog)/maximum electric-field in standard FeFETs for non-volatile memory application. The H-FeFET incorporates the threshold switch (TS) in the source of the FeFET, and is designed to exhibit a ferroelectric state-dependent volatile HRS to LRS transition (ION/IOFF >107)-during read, the TS turns ON only if the FeFET is in the low-VT SET state, and remains OFF if the FeFET is in the high-VT RESET state, thus, selectively suppressing the RESET read current. Leveraging this principle, the H-FeFET: a Demonstrates 77% higher MW and 1000× larger Iread,1/Iread,0 compared to the FeFET, at iso-Vprog (DC); (b) Enables 25% reduction in Vprog at iso-Iread,1/Iread,0 during pulse operation-facilitated by the 8× improvement in Iread,1/Iread,0; (c) Exhibits 2.5×reduction in programming power at iso-Iread,1/Iread,0 in the H-FeFET-based AND array architecture, as shown by simulations. Thus, the H-FeFET overcomes the FeFET design challenges while retaining its existing advantages, making it a promising candidate for nonvolatile memory applications.

Original languageEnglish (US)
Title of host publication2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages129-130
Number of pages2
ISBN (Electronic)9781538642160
DOIs
StatePublished - Oct 25 2018
Event38th IEEE Symposium on VLSI Technology, VLSI Technology 2018 - Honolulu, United States
Duration: Jun 18 2018Jun 22 2018

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
Volume2018-June
ISSN (Print)0743-1562

Other

Other38th IEEE Symposium on VLSI Technology, VLSI Technology 2018
CountryUnited States
CityHonolulu
Period6/18/186/22/18

Fingerprint

Computer programming
Switches
Data storage equipment
Electric potential
Ferroelectric materials
Electric fields

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Jerry, M., Aziz, A., Ni, K., Datta, S., Gupta, S. K., & Shukla, N. (2018). A threshold switch augmented hybrid-FeFET (H-FeFET) with enhanced read distinguishability and reduced programming voltage for non-volatile memory applications. In 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018 (pp. 129-130). [8510679] (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2018-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIT.2018.8510679
Jerry, M. ; Aziz, A. ; Ni, K. ; Datta, S. ; Gupta, Sumeet Kumar ; Shukla, N. / A threshold switch augmented hybrid-FeFET (H-FeFET) with enhanced read distinguishability and reduced programming voltage for non-volatile memory applications. 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 129-130 (Digest of Technical Papers - Symposium on VLSI Technology).
@inproceedings{ded4c907db5f46d2843161a955fc3d6c,
title = "A threshold switch augmented hybrid-FeFET (H-FeFET) with enhanced read distinguishability and reduced programming voltage for non-volatile memory applications",
abstract = "In this work, we demonstrate a novel Hybrid-FeFET (H-FeFET) that leverages the threshold switching characteristics of Ag/HfO2 to overcome the fundamental trade-off between memory window MW /read current ratio (Iread,1/Iread,0) , and program voltage (Vprog)/maximum electric-field in standard FeFETs for non-volatile memory application. The H-FeFET incorporates the threshold switch (TS) in the source of the FeFET, and is designed to exhibit a ferroelectric state-dependent volatile HRS to LRS transition (ION/IOFF >107)-during read, the TS turns ON only if the FeFET is in the low-VT SET state, and remains OFF if the FeFET is in the high-VT RESET state, thus, selectively suppressing the RESET read current. Leveraging this principle, the H-FeFET: a Demonstrates 77{\%} higher MW and 1000× larger Iread,1/Iread,0 compared to the FeFET, at iso-Vprog (DC); (b) Enables 25{\%} reduction in Vprog at iso-Iread,1/Iread,0 during pulse operation-facilitated by the 8× improvement in Iread,1/Iread,0; (c) Exhibits 2.5×reduction in programming power at iso-Iread,1/Iread,0 in the H-FeFET-based AND array architecture, as shown by simulations. Thus, the H-FeFET overcomes the FeFET design challenges while retaining its existing advantages, making it a promising candidate for nonvolatile memory applications.",
author = "M. Jerry and A. Aziz and K. Ni and S. Datta and Gupta, {Sumeet Kumar} and N. Shukla",
year = "2018",
month = "10",
day = "25",
doi = "10.1109/VLSIT.2018.8510679",
language = "English (US)",
series = "Digest of Technical Papers - Symposium on VLSI Technology",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "129--130",
booktitle = "2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018",
address = "United States",

}

Jerry, M, Aziz, A, Ni, K, Datta, S, Gupta, SK & Shukla, N 2018, A threshold switch augmented hybrid-FeFET (H-FeFET) with enhanced read distinguishability and reduced programming voltage for non-volatile memory applications. in 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018., 8510679, Digest of Technical Papers - Symposium on VLSI Technology, vol. 2018-June, Institute of Electrical and Electronics Engineers Inc., pp. 129-130, 38th IEEE Symposium on VLSI Technology, VLSI Technology 2018, Honolulu, United States, 6/18/18. https://doi.org/10.1109/VLSIT.2018.8510679

A threshold switch augmented hybrid-FeFET (H-FeFET) with enhanced read distinguishability and reduced programming voltage for non-volatile memory applications. / Jerry, M.; Aziz, A.; Ni, K.; Datta, S.; Gupta, Sumeet Kumar; Shukla, N.

2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 129-130 8510679 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2018-June).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - A threshold switch augmented hybrid-FeFET (H-FeFET) with enhanced read distinguishability and reduced programming voltage for non-volatile memory applications

AU - Jerry, M.

AU - Aziz, A.

AU - Ni, K.

AU - Datta, S.

AU - Gupta, Sumeet Kumar

AU - Shukla, N.

PY - 2018/10/25

Y1 - 2018/10/25

N2 - In this work, we demonstrate a novel Hybrid-FeFET (H-FeFET) that leverages the threshold switching characteristics of Ag/HfO2 to overcome the fundamental trade-off between memory window MW /read current ratio (Iread,1/Iread,0) , and program voltage (Vprog)/maximum electric-field in standard FeFETs for non-volatile memory application. The H-FeFET incorporates the threshold switch (TS) in the source of the FeFET, and is designed to exhibit a ferroelectric state-dependent volatile HRS to LRS transition (ION/IOFF >107)-during read, the TS turns ON only if the FeFET is in the low-VT SET state, and remains OFF if the FeFET is in the high-VT RESET state, thus, selectively suppressing the RESET read current. Leveraging this principle, the H-FeFET: a Demonstrates 77% higher MW and 1000× larger Iread,1/Iread,0 compared to the FeFET, at iso-Vprog (DC); (b) Enables 25% reduction in Vprog at iso-Iread,1/Iread,0 during pulse operation-facilitated by the 8× improvement in Iread,1/Iread,0; (c) Exhibits 2.5×reduction in programming power at iso-Iread,1/Iread,0 in the H-FeFET-based AND array architecture, as shown by simulations. Thus, the H-FeFET overcomes the FeFET design challenges while retaining its existing advantages, making it a promising candidate for nonvolatile memory applications.

AB - In this work, we demonstrate a novel Hybrid-FeFET (H-FeFET) that leverages the threshold switching characteristics of Ag/HfO2 to overcome the fundamental trade-off between memory window MW /read current ratio (Iread,1/Iread,0) , and program voltage (Vprog)/maximum electric-field in standard FeFETs for non-volatile memory application. The H-FeFET incorporates the threshold switch (TS) in the source of the FeFET, and is designed to exhibit a ferroelectric state-dependent volatile HRS to LRS transition (ION/IOFF >107)-during read, the TS turns ON only if the FeFET is in the low-VT SET state, and remains OFF if the FeFET is in the high-VT RESET state, thus, selectively suppressing the RESET read current. Leveraging this principle, the H-FeFET: a Demonstrates 77% higher MW and 1000× larger Iread,1/Iread,0 compared to the FeFET, at iso-Vprog (DC); (b) Enables 25% reduction in Vprog at iso-Iread,1/Iread,0 during pulse operation-facilitated by the 8× improvement in Iread,1/Iread,0; (c) Exhibits 2.5×reduction in programming power at iso-Iread,1/Iread,0 in the H-FeFET-based AND array architecture, as shown by simulations. Thus, the H-FeFET overcomes the FeFET design challenges while retaining its existing advantages, making it a promising candidate for nonvolatile memory applications.

UR - http://www.scopus.com/inward/record.url?scp=85056809691&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85056809691&partnerID=8YFLogxK

U2 - 10.1109/VLSIT.2018.8510679

DO - 10.1109/VLSIT.2018.8510679

M3 - Conference contribution

AN - SCOPUS:85056809691

T3 - Digest of Technical Papers - Symposium on VLSI Technology

SP - 129

EP - 130

BT - 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

Jerry M, Aziz A, Ni K, Datta S, Gupta SK, Shukla N. A threshold switch augmented hybrid-FeFET (H-FeFET) with enhanced read distinguishability and reduced programming voltage for non-volatile memory applications. In 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 129-130. 8510679. (Digest of Technical Papers - Symposium on VLSI Technology). https://doi.org/10.1109/VLSIT.2018.8510679