TY - GEN
T1 - A threshold switch augmented hybrid-FeFET (H-FeFET) with enhanced read distinguishability and reduced programming voltage for non-volatile memory applications
AU - Jerry, M.
AU - Aziz, A.
AU - Ni, K.
AU - Datta, S.
AU - Gupta, S. K.
AU - Shukla, N.
PY - 2018/10/25
Y1 - 2018/10/25
N2 - In this work, we demonstrate a novel Hybrid-FeFET (H-FeFET) that leverages the threshold switching characteristics of Ag/HfO2 to overcome the fundamental trade-off between memory window MW /read current ratio (Iread,1/Iread,0) , and program voltage (Vprog)/maximum electric-field in standard FeFETs for non-volatile memory application. The H-FeFET incorporates the threshold switch (TS) in the source of the FeFET, and is designed to exhibit a ferroelectric state-dependent volatile HRS to LRS transition (ION/IOFF >107)-during read, the TS turns ON only if the FeFET is in the low-VT SET state, and remains OFF if the FeFET is in the high-VT RESET state, thus, selectively suppressing the RESET read current. Leveraging this principle, the H-FeFET: a Demonstrates 77% higher MW and 1000× larger Iread,1/Iread,0 compared to the FeFET, at iso-Vprog (DC); (b) Enables 25% reduction in Vprog at iso-Iread,1/Iread,0 during pulse operation-facilitated by the 8× improvement in Iread,1/Iread,0; (c) Exhibits 2.5×reduction in programming power at iso-Iread,1/Iread,0 in the H-FeFET-based AND array architecture, as shown by simulations. Thus, the H-FeFET overcomes the FeFET design challenges while retaining its existing advantages, making it a promising candidate for nonvolatile memory applications.
AB - In this work, we demonstrate a novel Hybrid-FeFET (H-FeFET) that leverages the threshold switching characteristics of Ag/HfO2 to overcome the fundamental trade-off between memory window MW /read current ratio (Iread,1/Iread,0) , and program voltage (Vprog)/maximum electric-field in standard FeFETs for non-volatile memory application. The H-FeFET incorporates the threshold switch (TS) in the source of the FeFET, and is designed to exhibit a ferroelectric state-dependent volatile HRS to LRS transition (ION/IOFF >107)-during read, the TS turns ON only if the FeFET is in the low-VT SET state, and remains OFF if the FeFET is in the high-VT RESET state, thus, selectively suppressing the RESET read current. Leveraging this principle, the H-FeFET: a Demonstrates 77% higher MW and 1000× larger Iread,1/Iread,0 compared to the FeFET, at iso-Vprog (DC); (b) Enables 25% reduction in Vprog at iso-Iread,1/Iread,0 during pulse operation-facilitated by the 8× improvement in Iread,1/Iread,0; (c) Exhibits 2.5×reduction in programming power at iso-Iread,1/Iread,0 in the H-FeFET-based AND array architecture, as shown by simulations. Thus, the H-FeFET overcomes the FeFET design challenges while retaining its existing advantages, making it a promising candidate for nonvolatile memory applications.
UR - http://www.scopus.com/inward/record.url?scp=85056809691&partnerID=8YFLogxK
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U2 - 10.1109/VLSIT.2018.8510679
DO - 10.1109/VLSIT.2018.8510679
M3 - Conference contribution
AN - SCOPUS:85056809691
T3 - Digest of Technical Papers - Symposium on VLSI Technology
SP - 129
EP - 130
BT - 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 38th IEEE Symposium on VLSI Technology, VLSI Technology 2018
Y2 - 18 June 2018 through 22 June 2018
ER -