In this paper we present a new, very fine grain associative architecture. Very fine grain architectures are especially suited for problems with a high degree of parallelism. However, to maintain their fine graininess most fine grain processors are relatively inflexible. Any attempt to increase flexibility increases processor complexity and, thereby, increases graininess. The architecture we present in this paper maintains both a high degree of flexibility and fine graininess. This is done by reducing each processor to an associative memory cell. However, unlike other associative memory processors, ours uses a two-dimensional interconnect and a physically compact memory structure. Arithmetic operations are based on the use of a redundant number system. These features provide a high level of performance. This is particularly true for certain two-dimensional problems which we show can be solved very efficiently on our architecture.
All Science Journal Classification (ASJC) codes
- Theoretical Computer Science
- Hardware and Architecture
- Computational Theory and Mathematics