A write update cache coherence protocol for MIN-based multiprocessors with accessibility-based split caches

M. S. Algudady, C. R. Das, M. J. Thazhuthaveetil

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

The authors present a cache coherence protocol for MIN-based multiprocessors with two distinct private caches: private-block caches containing information private to a processor and shared-block caches containing data accessible by all processors. The protocol utilizes a coherence control bus (snooping) for connecting all shared-block cache controllers. Timing problems due to variable transit delay through the MIN are dealt with by introducing transient states in the protocol. Assuming homogeneity of all nodes, a single-node queuing model is developed to analyze the system performance. This model is solved using the mean-value-analysis technique with protocol state probabilities, and few communication delays as input parameters. System performance measures are verified through simulation.

Original languageEnglish (US)
Title of host publicationProc Supercomput 90
PublisherPubl by IEEE
Pages544-553
Number of pages10
ISBN (Print)0818620560
StatePublished - Dec 1 1990
EventProceedings of Supercomputing '90 -
Duration: Nov 12 1990Nov 16 1990

Publication series

NameProc Supercomput 90

Other

OtherProceedings of Supercomputing '90
Period11/12/9011/16/90

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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