An accurate and efficient stacking effect macro-model for leakage power in sub-100nm circuits is presented in this paper. Leakage power, including subthreshold leakage power and gate leakage power, is becoming more significant compared to dynamic power when technology scaling down below 100nm. Consequently, fast and accurate leakage power estimation models, which are strongly dependent on precise modeling of the stacking effect on subthreshold leakage and gate leakage, are vital for evaluating optimizations. In this work, making use of the interactions between subthreshold leakage and gate leakage, we focus our attention on analyzing the effects of transistor stacking on gate leakage between the channel and the gate and that between the drain/source and the gate. The contribution of the latter has been largely ignored in prior work, while our work shows that it is an important factor. Based on the stacking effect analysis, we have proposed a new best input vector to reduce the total leakage power; and an efficient and accurate leakage power estimation macro-model which achieves a mean error of 3.1% when compared to HSPICE.