Activation Energies for Oxide- and Interface-Trap Charge Generation Due to Negative-Bias Temperature Stress of Si-Capped SiGe-pMOSFETs

Guo Xing Duan, Jordan Hatchtel, Xiao Shen, En Xia Zhang, Cher Xuan Zhang, Blair Richard Tuttle, Daniel M. Fleetwood, Ronald D. Schrimpf, Robert A. Reed, Jacopo Franco, Dimitri Linten, Jerome Mitard, Liesbeth Witters, Nadine Collaert, Matthew F. Chisholm, Sokrates T. Pantelides

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

We investigate negative-bias temperature instabilities in SiGe pMOSFETs with SiO 2/HfO 2 gate dielectrics. The measured activation energies for interface-trap charge buildup during negative-bias temperature stress are lower for SiGe channel pMOSFETs with SiO 2/HfO 2 gate dielectrics and Si capping layers than for conventional Si channel pMOSFETs with SiO 2 gate dielectrics. Electron energy loss spectroscopy and scanning transmission electron microscopy images demonstrate that Ge atoms can diffuse from the SiGe layer into the Si capping layer, which is adjacent to the SiO 2/HfO 2 gate dielectric. Density functional calculations show that these Ge atoms reduce the strength of nearby Si-H bonds and that Ge-H bond energies are still lower, thereby reducing the activation energy for interface-trap generation for the SiGe devices. Activation energies for oxide-trap charge buildup during negative-bias temperature stress are similarly small for SiGe pMOSFETs with SiO 2/HfO 2 gate dielectrics and Si pMOSFETs with SiO 2 gate dielectrics, suggesting that, in both cases, the oxide-trap charge buildup likely is rate-limited by hole tunneling into the near-interfacial SiO 2.

Original languageEnglish (US)
Article number7118163
Pages (from-to)352-358
Number of pages7
JournalIEEE Transactions on Device and Materials Reliability
Volume15
Issue number3
DOIs
StatePublished - Sep 1 2015

Fingerprint

Gate dielectrics
Oxides
Activation energy
Temperature
Atoms
Electron energy loss spectroscopy
Density functional theory
Transmission electron microscopy
Scanning electron microscopy

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Safety, Risk, Reliability and Quality
  • Electrical and Electronic Engineering

Cite this

Duan, Guo Xing ; Hatchtel, Jordan ; Shen, Xiao ; Zhang, En Xia ; Zhang, Cher Xuan ; Tuttle, Blair Richard ; Fleetwood, Daniel M. ; Schrimpf, Ronald D. ; Reed, Robert A. ; Franco, Jacopo ; Linten, Dimitri ; Mitard, Jerome ; Witters, Liesbeth ; Collaert, Nadine ; Chisholm, Matthew F. ; Pantelides, Sokrates T. / Activation Energies for Oxide- and Interface-Trap Charge Generation Due to Negative-Bias Temperature Stress of Si-Capped SiGe-pMOSFETs. In: IEEE Transactions on Device and Materials Reliability. 2015 ; Vol. 15, No. 3. pp. 352-358.
@article{ac899d085f51474b9b9c6ca0b04bbbe6,
title = "Activation Energies for Oxide- and Interface-Trap Charge Generation Due to Negative-Bias Temperature Stress of Si-Capped SiGe-pMOSFETs",
abstract = "We investigate negative-bias temperature instabilities in SiGe pMOSFETs with SiO 2/HfO 2 gate dielectrics. The measured activation energies for interface-trap charge buildup during negative-bias temperature stress are lower for SiGe channel pMOSFETs with SiO 2/HfO 2 gate dielectrics and Si capping layers than for conventional Si channel pMOSFETs with SiO 2 gate dielectrics. Electron energy loss spectroscopy and scanning transmission electron microscopy images demonstrate that Ge atoms can diffuse from the SiGe layer into the Si capping layer, which is adjacent to the SiO 2/HfO 2 gate dielectric. Density functional calculations show that these Ge atoms reduce the strength of nearby Si-H bonds and that Ge-H bond energies are still lower, thereby reducing the activation energy for interface-trap generation for the SiGe devices. Activation energies for oxide-trap charge buildup during negative-bias temperature stress are similarly small for SiGe pMOSFETs with SiO 2/HfO 2 gate dielectrics and Si pMOSFETs with SiO 2 gate dielectrics, suggesting that, in both cases, the oxide-trap charge buildup likely is rate-limited by hole tunneling into the near-interfacial SiO 2.",
author = "Duan, {Guo Xing} and Jordan Hatchtel and Xiao Shen and Zhang, {En Xia} and Zhang, {Cher Xuan} and Tuttle, {Blair Richard} and Fleetwood, {Daniel M.} and Schrimpf, {Ronald D.} and Reed, {Robert A.} and Jacopo Franco and Dimitri Linten and Jerome Mitard and Liesbeth Witters and Nadine Collaert and Chisholm, {Matthew F.} and Pantelides, {Sokrates T.}",
year = "2015",
month = "9",
day = "1",
doi = "10.1109/TDMR.2015.2442152",
language = "English (US)",
volume = "15",
pages = "352--358",
journal = "IEEE Transactions on Device and Materials Reliability",
issn = "1530-4388",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "3",

}

Duan, GX, Hatchtel, J, Shen, X, Zhang, EX, Zhang, CX, Tuttle, BR, Fleetwood, DM, Schrimpf, RD, Reed, RA, Franco, J, Linten, D, Mitard, J, Witters, L, Collaert, N, Chisholm, MF & Pantelides, ST 2015, 'Activation Energies for Oxide- and Interface-Trap Charge Generation Due to Negative-Bias Temperature Stress of Si-Capped SiGe-pMOSFETs', IEEE Transactions on Device and Materials Reliability, vol. 15, no. 3, 7118163, pp. 352-358. https://doi.org/10.1109/TDMR.2015.2442152

Activation Energies for Oxide- and Interface-Trap Charge Generation Due to Negative-Bias Temperature Stress of Si-Capped SiGe-pMOSFETs. / Duan, Guo Xing; Hatchtel, Jordan; Shen, Xiao; Zhang, En Xia; Zhang, Cher Xuan; Tuttle, Blair Richard; Fleetwood, Daniel M.; Schrimpf, Ronald D.; Reed, Robert A.; Franco, Jacopo; Linten, Dimitri; Mitard, Jerome; Witters, Liesbeth; Collaert, Nadine; Chisholm, Matthew F.; Pantelides, Sokrates T.

In: IEEE Transactions on Device and Materials Reliability, Vol. 15, No. 3, 7118163, 01.09.2015, p. 352-358.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Activation Energies for Oxide- and Interface-Trap Charge Generation Due to Negative-Bias Temperature Stress of Si-Capped SiGe-pMOSFETs

AU - Duan, Guo Xing

AU - Hatchtel, Jordan

AU - Shen, Xiao

AU - Zhang, En Xia

AU - Zhang, Cher Xuan

AU - Tuttle, Blair Richard

AU - Fleetwood, Daniel M.

AU - Schrimpf, Ronald D.

AU - Reed, Robert A.

AU - Franco, Jacopo

AU - Linten, Dimitri

AU - Mitard, Jerome

AU - Witters, Liesbeth

AU - Collaert, Nadine

AU - Chisholm, Matthew F.

AU - Pantelides, Sokrates T.

PY - 2015/9/1

Y1 - 2015/9/1

N2 - We investigate negative-bias temperature instabilities in SiGe pMOSFETs with SiO 2/HfO 2 gate dielectrics. The measured activation energies for interface-trap charge buildup during negative-bias temperature stress are lower for SiGe channel pMOSFETs with SiO 2/HfO 2 gate dielectrics and Si capping layers than for conventional Si channel pMOSFETs with SiO 2 gate dielectrics. Electron energy loss spectroscopy and scanning transmission electron microscopy images demonstrate that Ge atoms can diffuse from the SiGe layer into the Si capping layer, which is adjacent to the SiO 2/HfO 2 gate dielectric. Density functional calculations show that these Ge atoms reduce the strength of nearby Si-H bonds and that Ge-H bond energies are still lower, thereby reducing the activation energy for interface-trap generation for the SiGe devices. Activation energies for oxide-trap charge buildup during negative-bias temperature stress are similarly small for SiGe pMOSFETs with SiO 2/HfO 2 gate dielectrics and Si pMOSFETs with SiO 2 gate dielectrics, suggesting that, in both cases, the oxide-trap charge buildup likely is rate-limited by hole tunneling into the near-interfacial SiO 2.

AB - We investigate negative-bias temperature instabilities in SiGe pMOSFETs with SiO 2/HfO 2 gate dielectrics. The measured activation energies for interface-trap charge buildup during negative-bias temperature stress are lower for SiGe channel pMOSFETs with SiO 2/HfO 2 gate dielectrics and Si capping layers than for conventional Si channel pMOSFETs with SiO 2 gate dielectrics. Electron energy loss spectroscopy and scanning transmission electron microscopy images demonstrate that Ge atoms can diffuse from the SiGe layer into the Si capping layer, which is adjacent to the SiO 2/HfO 2 gate dielectric. Density functional calculations show that these Ge atoms reduce the strength of nearby Si-H bonds and that Ge-H bond energies are still lower, thereby reducing the activation energy for interface-trap generation for the SiGe devices. Activation energies for oxide-trap charge buildup during negative-bias temperature stress are similarly small for SiGe pMOSFETs with SiO 2/HfO 2 gate dielectrics and Si pMOSFETs with SiO 2 gate dielectrics, suggesting that, in both cases, the oxide-trap charge buildup likely is rate-limited by hole tunneling into the near-interfacial SiO 2.

UR - http://www.scopus.com/inward/record.url?scp=84941006891&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84941006891&partnerID=8YFLogxK

U2 - 10.1109/TDMR.2015.2442152

DO - 10.1109/TDMR.2015.2442152

M3 - Article

VL - 15

SP - 352

EP - 358

JO - IEEE Transactions on Device and Materials Reliability

JF - IEEE Transactions on Device and Materials Reliability

SN - 1530-4388

IS - 3

M1 - 7118163

ER -