Adapting instruction level parallelism for optimizing leakage in VLIW architectures

H. S. Kim, Vijaykrishnan Narayanan, Mahmut Kandemir, Mary Jane Irwin

Research output: Contribution to journalConference article

11 Citations (Scopus)

Abstract

Due to ever increasing number of transistors and decreasing threshold voltages, leakage energy consumption is expected to play a decisive role in the next generation circuits. We believe that software support is a must to exploit available leakage control mechanisms. In this paper, we present and evaluate a compiler-oriented leakage optimization strategy based on tuning IPC (instructions -issued- per cycle) at a loop-level granularity according to the needs of application. Once a suitable IPC is selected for each loop, our strategy turns off unused or not frequently used integer ALUs to save leakage energy. Our preliminary results indicate that our technique can reduce up to 38% of the functional unit leakage energy across a range of VLIW configurations. Our results also show that our loop based IPC detection strategy gives better energy-delay product than finer-granularity (basic block level) and coarser-granularity (whole application level) IPC detection schemes.

Original languageEnglish (US)
Pages (from-to)275-283
Number of pages9
JournalACM SIGPLAN Notices
Volume38
Issue number7
DOIs
StatePublished - Jan 1 2003
EventProceedings of the 2003 ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems - San Diego, CA, United States
Duration: Jun 11 2003Jun 13 2003

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Very long instruction word architecture
Threshold voltage
Transistors
Energy utilization
Tuning
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design

Cite this

@article{ec6f8f2e3f8f46ccb528ad4596aa53f2,
title = "Adapting instruction level parallelism for optimizing leakage in VLIW architectures",
abstract = "Due to ever increasing number of transistors and decreasing threshold voltages, leakage energy consumption is expected to play a decisive role in the next generation circuits. We believe that software support is a must to exploit available leakage control mechanisms. In this paper, we present and evaluate a compiler-oriented leakage optimization strategy based on tuning IPC (instructions -issued- per cycle) at a loop-level granularity according to the needs of application. Once a suitable IPC is selected for each loop, our strategy turns off unused or not frequently used integer ALUs to save leakage energy. Our preliminary results indicate that our technique can reduce up to 38{\%} of the functional unit leakage energy across a range of VLIW configurations. Our results also show that our loop based IPC detection strategy gives better energy-delay product than finer-granularity (basic block level) and coarser-granularity (whole application level) IPC detection schemes.",
author = "Kim, {H. S.} and Vijaykrishnan Narayanan and Mahmut Kandemir and Irwin, {Mary Jane}",
year = "2003",
month = "1",
day = "1",
doi = "10.1145/780731.780770",
language = "English (US)",
volume = "38",
pages = "275--283",
journal = "ACM SIGPLAN Notices",
issn = "1523-2867",
publisher = "Association for Computing Machinery (ACM)",
number = "7",

}

Adapting instruction level parallelism for optimizing leakage in VLIW architectures. / Kim, H. S.; Narayanan, Vijaykrishnan; Kandemir, Mahmut; Irwin, Mary Jane.

In: ACM SIGPLAN Notices, Vol. 38, No. 7, 01.01.2003, p. 275-283.

Research output: Contribution to journalConference article

TY - JOUR

T1 - Adapting instruction level parallelism for optimizing leakage in VLIW architectures

AU - Kim, H. S.

AU - Narayanan, Vijaykrishnan

AU - Kandemir, Mahmut

AU - Irwin, Mary Jane

PY - 2003/1/1

Y1 - 2003/1/1

N2 - Due to ever increasing number of transistors and decreasing threshold voltages, leakage energy consumption is expected to play a decisive role in the next generation circuits. We believe that software support is a must to exploit available leakage control mechanisms. In this paper, we present and evaluate a compiler-oriented leakage optimization strategy based on tuning IPC (instructions -issued- per cycle) at a loop-level granularity according to the needs of application. Once a suitable IPC is selected for each loop, our strategy turns off unused or not frequently used integer ALUs to save leakage energy. Our preliminary results indicate that our technique can reduce up to 38% of the functional unit leakage energy across a range of VLIW configurations. Our results also show that our loop based IPC detection strategy gives better energy-delay product than finer-granularity (basic block level) and coarser-granularity (whole application level) IPC detection schemes.

AB - Due to ever increasing number of transistors and decreasing threshold voltages, leakage energy consumption is expected to play a decisive role in the next generation circuits. We believe that software support is a must to exploit available leakage control mechanisms. In this paper, we present and evaluate a compiler-oriented leakage optimization strategy based on tuning IPC (instructions -issued- per cycle) at a loop-level granularity according to the needs of application. Once a suitable IPC is selected for each loop, our strategy turns off unused or not frequently used integer ALUs to save leakage energy. Our preliminary results indicate that our technique can reduce up to 38% of the functional unit leakage energy across a range of VLIW configurations. Our results also show that our loop based IPC detection strategy gives better energy-delay product than finer-granularity (basic block level) and coarser-granularity (whole application level) IPC detection schemes.

UR - http://www.scopus.com/inward/record.url?scp=1442288679&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=1442288679&partnerID=8YFLogxK

U2 - 10.1145/780731.780770

DO - 10.1145/780731.780770

M3 - Conference article

VL - 38

SP - 275

EP - 283

JO - ACM SIGPLAN Notices

JF - ACM SIGPLAN Notices

SN - 1523-2867

IS - 7

ER -