Adapting instruction level parallelism for optimizing leakage in VLIW architectures

H. S. Kim, Vijaykrishnan Narayanan, Mahmut Kandemir, Mary Jane Irwin

Research output: Contribution to conferencePaper

22 Scopus citations

Abstract

Due to ever increasing number of transistors and decreasing threshold voltages, leakage energy consumption is expected to play a decisive role in the next generation circuits. We believe that software support is a must to exploit available leakage control mechanisms. In this paper, we present and evaluate a compiler-oriented leakage optimization strategy based on tuning IPC (instructions-issued-per cycle) at a loop-level granularity according to the needs of application. Once a suitable IPC is selected for each loop, our strategy turns off unused or not frequently used integer ALUs to save leakage energy. Our preliminary results indicate that our technique can reduce up to 38% of the functional unit leakage energy across a range of VLIW configurations. Our results also show that our loop based IPC detection strategy gives better energy-delay product than finer-granularity (basic block level) and coarser-granularity (whole application level) IPC detection schemes.

Original languageEnglish (US)
Pages275-283
Number of pages9
StatePublished - Nov 19 2003
EventProceedings of the 2003 ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems - San Diego, CA, United States
Duration: Jun 11 2003Jun 13 2003

Conference

ConferenceProceedings of the 2003 ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems
CountryUnited States
CitySan Diego, CA
Period6/11/036/13/03

All Science Journal Classification (ASJC) codes

  • Software

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    Kim, H. S., Narayanan, V., Kandemir, M., & Irwin, M. J. (2003). Adapting instruction level parallelism for optimizing leakage in VLIW architectures. 275-283. Paper presented at Proceedings of the 2003 ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems, San Diego, CA, United States.