Address register assignment for reducing code size

Mahmut Kandemir, Mary Jane Irwin, G. Chen, J. Ramanujam

Research output: Contribution to journalArticle

3 Scopus citations


In DSP processors, minimizing the amount of address calculations is critical for reducing code size and improving performance since studies of programs have shown that instructions that manipulate address registers constitute a significant portion of the overall instruction count (up to 55%). This work presents a compiler-based optimization strategy to reduce the code size in embedded systems. Our strategy maximizes the use of indirect addressing modes with post-increment and post-decrement capabilities available in DSP processors. These modes can be exploited by ensuring that successive references to variables access consecutive memory locations. To achieve this spatial locality, our approach uses both access pattern modification (program code restructuring) and memory storage reordering (data layout restructuring).

Original languageEnglish (US)
Pages (from-to)273-289
Number of pages17
JournalLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Publication statusPublished - Dec 1 2003


All Science Journal Classification (ASJC) codes

  • Theoretical Computer Science
  • Computer Science(all)

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