TY - JOUR
T1 - Advancing Nonvolatile Computing with Nonvolatile NCFET Latches and Flip-Flops
AU - Li, Xueqing
AU - George, Sumitha
AU - Ma, Kaisheng
AU - Tsai, Wei Yu
AU - Aziz, Ahmedullah
AU - Sampson, John
AU - Gupta, Sumeet Kumar
AU - Chang, Meng Fan
AU - Liu, Yongpan
AU - Datta, Suman
AU - Narayanan, Vijaykrishnan
N1 - Funding Information:
The work of K. Ma was supported by NSF ASSIST.
Funding Information:
Manuscript received December 7, 2016; revised April 19, 2017; accepted May 2, 2017. Date of publication June 2, 2017; date of current version October 24, 2017. This work was supported in part by LEAST, a funded center of STARnet, a Semiconductor Research Corporation (SRC) program sponsored by MARCO and DARPA, in part by GRC under Grant 2657.001, and in part by NSFC under Grant 61674094. The work of K. Ma was supported by NSF ASSIST. This paper was recommended by Associate Editor M. Alioto. (Corresponding authors: Xueqing Li; John Sampson.) X. Li, S. George, K. Ma, W.-Y. Tsai, A. Aziz, J. Sampson, S. K. Gupta, and V. Narayanan are with the School of Electrical Engineering and Computer Science, The Pennsylvania State University, University Park, PA 16802 USA (e-mail: lixueq@cse.psu.edu; sug241@cse.psu.edu; kxm505@cse.psu.edu; wzt114@cse.psu.edu; afa5191@psu.edu; sampson@ cse.psu.edu; skg157@engr.psu.edu; vijay@cse.psu.edu).
Publisher Copyright:
© 2012 IEEE.
PY - 2017/11
Y1 - 2017/11
N2 - Nonvolatile computing has been proven to be effective in dealing with power supply outages for on-chip check-pointing in emerging energy-harvesting Internet-of-Things applications. It also plays an important role in power-gating to cut off leakage power for higher energy efficiency. However, existing on-chip state backup solutions for D flip-flop (DFF) have a bottleneck of significant energy and/or latency penalties which limit the overall energy efficiency and computing progress. Meanwhile, these solutions rely on external control that limits compatibility and increases system complexity. This paper proposes an approach to fundamentally advancing the nonvolatile computing paradigm by intrinsically nonvolatile area-efficient latches and flip-flops designs using negative capacitance FET. These designs consume fJ-level energy and ns-level intrinsic latency for a backup plus restore operation, e.g., 2.4 fJ in energy and 1.1 ns in time for one proposed nonvolatile DFF with a supply power of 0.80 V.
AB - Nonvolatile computing has been proven to be effective in dealing with power supply outages for on-chip check-pointing in emerging energy-harvesting Internet-of-Things applications. It also plays an important role in power-gating to cut off leakage power for higher energy efficiency. However, existing on-chip state backup solutions for D flip-flop (DFF) have a bottleneck of significant energy and/or latency penalties which limit the overall energy efficiency and computing progress. Meanwhile, these solutions rely on external control that limits compatibility and increases system complexity. This paper proposes an approach to fundamentally advancing the nonvolatile computing paradigm by intrinsically nonvolatile area-efficient latches and flip-flops designs using negative capacitance FET. These designs consume fJ-level energy and ns-level intrinsic latency for a backup plus restore operation, e.g., 2.4 fJ in energy and 1.1 ns in time for one proposed nonvolatile DFF with a supply power of 0.80 V.
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U2 - 10.1109/TCSI.2017.2702741
DO - 10.1109/TCSI.2017.2702741
M3 - Article
AN - SCOPUS:85034014911
SN - 1549-8328
VL - 64
SP - 2907
EP - 2919
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
IS - 11
M1 - 7938368
ER -
