TY - GEN
T1 - All-organic active matrix OLED display
AU - Zhou, Lisong
AU - Park, Sungkyu
AU - Bai, Bo
AU - Sun, Jie
AU - Wu, Sheng Chu
AU - Jackson, Thomas Nelson
AU - Nelson, Shelby
AU - Freeman, Diane
AU - Hong, Yongtaek
PY - 2005/12/1
Y1 - 2005/12/1
N2 - There has been great deal of interest in and research on organic light-emitting diodes (OLEDs) because of the possibility of thinner, lighter, faster and more power efficient displays. Several active matrix OLED displays have been demonstrated on both glass and polymeric substrates. To date, most active matrix OLED displays have used polysilicon or amorphous silicon thin film transistors (TFTs) as the active elements. Pentacene organic thin film transistors (OTFTs), with performance comparable to those of a-Si:H, are of interest because of the possibility of reduced processing cost compared to a-Si:H and perhaps also roll-to-roll manufacturing. A small (8×8 pixel) pentacene TFT driven OLED display has been demonstrated [1], however a range of issues including dielectric integrity, device passivation techniques, and TFT uniformity, still need to be addressed. We report here on 48 × 48 pixels pentacene TFT driven active-matrix OLED displays on glass substrate. To our best knowledge these are the largest pentacene TFT driven displays. The displays reported here used a simple two transistor per pixel drive scheme (figure 1) with a pixel pitch of 500 μm and an aperture ratio of 0.54. The drive and select transistors had a W/L ratio of 10 (200 μm/20 μm) and 1 (20 μm/20 μm), respectively and the storage capacitor is 1.2pF. Figure 2 shows a cross section of the pixel, including select OTFT, storage capacitor, drive OTFT and OLED. The substrate is 0.7mm glass coated with 85nm ITO film. First, the ITO is patterned by photolithography and wet etching. A 50nm chrome gate layer was then deposited by sputtering and patterned by wet etching. A 300nm thick ion-beam sputtered SiO 2, was used as the gate dielectric and patterned by lift-off. A 100nm platinum source-drain layer was deposited by sputtering and patterned by lift-off. After vapor treatment in octadecyltrichlorosilane a 50nm pentacene layer was thermally evaporated at 60°C at a rate of 0.1-0.5Å/s. To pattern the pentacene active layer photo-sensitized polyvinyl alcohol (PVA) water-based photoresist was used to mask the active region and field pentacene was removed by oxygen plasma etching. Because residual water trapped in the PVA can reduce OLED lifetime the patterned OTFTs were encapsulated by a 1μm thick parylene layer deposited at room temperature and patterned by photolithography and RIE dry etching. The OLED stack was then deposited onto the OTFT backplane through a shadow mask by thermal evaporation. The OLED organic layers were: 75 nm 4,4′-bis[N-(1-napthyl)-N-Phenyl-amino] biphenyl (α-NPD) as the hole transport layer, and 75 nm tris (8-hydroxyquinoline) aluminum (Alq 3) as the electron transport layer. Next, a 220 nm magnesium/silver cathode was deposited through shadow mask. Finally, the OLED display area was encapsulated with glass sealed by UV cured epoxy. Figure 3 shows the typical characteristics of the drive OTFT on the backplane, from which, the saturation mobility, threshold voltage, on/off ratio and sub-threshold slope can be extracted as 0.6cm 2/V-s, 12.6 V, > 10 7, and 2.5V/Dec, respectively. Since OLEDs are current driven light-emitting devices, i.e., the brightness is proportional to the current, OTFT uniformity is critical to the OLED display. Figure 4 shows the results for a 105 OTFT uniformity test array (W/L=200/20μm). The array yield is 94% with an average threshold voltage of 13.7 V and a standard deviation of 0.78 V, and an average field-effect mobility of 0.584 cm 2/V-s and a standard deviation of 0.017 cm 2/V-s. Figure 5 shows a pentacene OTFT driven OLED pixel and figure 6 shows a 48 × 48 array driven with all the pixels in the on (V SELECT= 0V and V DATA = 0V) and off (V SELECT = 40V, V DATA = 30V) state, at V DD = 20V, V CA = -10V. Although the defect density is large basic display function is demonstrated. These results suggest that that pentacene OTFT backplanes are viable candidates for active-matrix OLED displays.
AB - There has been great deal of interest in and research on organic light-emitting diodes (OLEDs) because of the possibility of thinner, lighter, faster and more power efficient displays. Several active matrix OLED displays have been demonstrated on both glass and polymeric substrates. To date, most active matrix OLED displays have used polysilicon or amorphous silicon thin film transistors (TFTs) as the active elements. Pentacene organic thin film transistors (OTFTs), with performance comparable to those of a-Si:H, are of interest because of the possibility of reduced processing cost compared to a-Si:H and perhaps also roll-to-roll manufacturing. A small (8×8 pixel) pentacene TFT driven OLED display has been demonstrated [1], however a range of issues including dielectric integrity, device passivation techniques, and TFT uniformity, still need to be addressed. We report here on 48 × 48 pixels pentacene TFT driven active-matrix OLED displays on glass substrate. To our best knowledge these are the largest pentacene TFT driven displays. The displays reported here used a simple two transistor per pixel drive scheme (figure 1) with a pixel pitch of 500 μm and an aperture ratio of 0.54. The drive and select transistors had a W/L ratio of 10 (200 μm/20 μm) and 1 (20 μm/20 μm), respectively and the storage capacitor is 1.2pF. Figure 2 shows a cross section of the pixel, including select OTFT, storage capacitor, drive OTFT and OLED. The substrate is 0.7mm glass coated with 85nm ITO film. First, the ITO is patterned by photolithography and wet etching. A 50nm chrome gate layer was then deposited by sputtering and patterned by wet etching. A 300nm thick ion-beam sputtered SiO 2, was used as the gate dielectric and patterned by lift-off. A 100nm platinum source-drain layer was deposited by sputtering and patterned by lift-off. After vapor treatment in octadecyltrichlorosilane a 50nm pentacene layer was thermally evaporated at 60°C at a rate of 0.1-0.5Å/s. To pattern the pentacene active layer photo-sensitized polyvinyl alcohol (PVA) water-based photoresist was used to mask the active region and field pentacene was removed by oxygen plasma etching. Because residual water trapped in the PVA can reduce OLED lifetime the patterned OTFTs were encapsulated by a 1μm thick parylene layer deposited at room temperature and patterned by photolithography and RIE dry etching. The OLED stack was then deposited onto the OTFT backplane through a shadow mask by thermal evaporation. The OLED organic layers were: 75 nm 4,4′-bis[N-(1-napthyl)-N-Phenyl-amino] biphenyl (α-NPD) as the hole transport layer, and 75 nm tris (8-hydroxyquinoline) aluminum (Alq 3) as the electron transport layer. Next, a 220 nm magnesium/silver cathode was deposited through shadow mask. Finally, the OLED display area was encapsulated with glass sealed by UV cured epoxy. Figure 3 shows the typical characteristics of the drive OTFT on the backplane, from which, the saturation mobility, threshold voltage, on/off ratio and sub-threshold slope can be extracted as 0.6cm 2/V-s, 12.6 V, > 10 7, and 2.5V/Dec, respectively. Since OLEDs are current driven light-emitting devices, i.e., the brightness is proportional to the current, OTFT uniformity is critical to the OLED display. Figure 4 shows the results for a 105 OTFT uniformity test array (W/L=200/20μm). The array yield is 94% with an average threshold voltage of 13.7 V and a standard deviation of 0.78 V, and an average field-effect mobility of 0.584 cm 2/V-s and a standard deviation of 0.017 cm 2/V-s. Figure 5 shows a pentacene OTFT driven OLED pixel and figure 6 shows a 48 × 48 array driven with all the pixels in the on (V SELECT= 0V and V DATA = 0V) and off (V SELECT = 40V, V DATA = 30V) state, at V DD = 20V, V CA = -10V. Although the defect density is large basic display function is demonstrated. These results suggest that that pentacene OTFT backplanes are viable candidates for active-matrix OLED displays.
UR - http://www.scopus.com/inward/record.url?scp=33751345335&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=33751345335&partnerID=8YFLogxK
U2 - 10.1109/DRC.2005.1553092
DO - 10.1109/DRC.2005.1553092
M3 - Conference contribution
AN - SCOPUS:33751345335
SN - 0780390407
SN - 9780780390409
T3 - Device Research Conference - Conference Digest, DRC
SP - 137
EP - 138
BT - 63rd Device Research Conference Digest, DRC'05
T2 - 63rd Device Research Conference, DRC'05
Y2 - 20 June 2005 through 22 June 2005
ER -