Alternative architecture for on-chip global interconnect: Segmented bus power modeling

Yan Zhang, Wu Ye, Mary Jane Irwin

Research output: Contribution to journalConference articlepeer-review

22 Scopus citations

Abstract

On-chip interconnect power consumption has become an important issue as technology quickly scales down and the industry embraces system-on-a-chip (SOC). The simple bus structure may become a serious bottleneck in reducing the total chip power consumption and increasing performance due to transmission line effects. Alternative interconnect structures should be considered under this circumstances. This paper models the power consumption of both a global data bus and the proposed segmented bus for a commercial chip at the behavioral level. The chip is an integration of a 16-bit DSP and a 32-bit RISC microcontroller. The power measurements of both bus structures at different technology feature size levels are reported for a set of standard signal processing benchmarks.

Original languageEnglish (US)
Pages (from-to)1062-1065
Number of pages4
JournalConference Record of the Asilomar Conference on Signals, Systems and Computers
Volume2
StatePublished - Dec 1 1998
EventProceedings of the 1998 32nd Asilomar Conference on Signals, Systems & Computers. Part 1 (of 2) - Pacific Grove, CA, USA
Duration: Nov 1 1998Nov 4 1998

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Computer Networks and Communications

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