Electrostatic discharge (ESD) testing of integrated circuits (ICs) is necessary to ensure that the products can withstand several types of ESD threats, including those encountered in the factory and in the field. This study discusses the testing of components with electrostatic stress waveforms that were originally designed for predicting system failures in the field. IC manufacturers are struggling to obtain reliable data when applying system tests to their components due to interface and repeatability problems found with this form of evaluation. To alleviate these problems and some of the confusion, a new test methodology has been designed and implemented. It is used for testing individual components that have pins that are to be connected to the external ports on a completed design. This study reports on a new method that solves these IC testing problems and compares it to the current approach most often employed.
|Original language||English (US)|
|Number of pages||9|
|Journal||IET Science, Measurement and Technology|
|State||Published - Jul 1 2010|
All Science Journal Classification (ASJC) codes
- Atomic and Molecular Physics, and Optics
- Electrical and Electronic Engineering