An accuracy tunable non-boolean co-processor using coupled nano-oscillators

Neel Gala, Sarada Krithivasan, Wei Yu Tsai, Xueqing Li, Vijaykrishnan Narayanan, V. Kamakoti

Research output: Contribution to journalArticle

1 Scopus citations

Abstract

As we enter an era witnessing the closer end of Dennard scaling, where further reduction in power supplyvoltage to reduce power consumption becomes more challenging in conventional systems, a goal of developing a system capable of performing large computations with minimal area and power overheads needs more optimization aspects. A rigorous exploration of alternate computing techniques, which can mitigate the limitations of Complementary Metal-Oxide Semiconductor (CMOS) technology scaling and conventional Boolean systems, is imperative. Reflecting on these lines of thought, in this article we explore the potential of non-Boolean computing employing nano-oscillators for performing varied functions. We use a two coupled nano-oscillator as our basic computational model and propose an architecture for a non-Boolean coupled oscillator based co-processor capable of executing certain functions that are commonly used across a variety of approximate application domains. The proposed architecture includes an accuracy tunable knob, which can be tuned by the programmer at runtime. The functionality of the proposed co-processor is verified using a soft coupled oscillator model based on Kuramoto oscillators. The article also demonstrates how real-world applications such as Vector Quantization, Digit Recognition, Structural Health Monitoring, and the like, can be deployed on the proposed model. The proposed co-processor architecture is generic in nature and can be implemented using any of the existing modern day nano-oscillator technologies such as Resonant Body Transistors (RBTs), Spin-Torque Nano-Oscillators (STNOs), and Metal-Insulator Transition (MITs). In this article, we perform a validation of the proposed architecture using the HyperField Effect Transistor (FET) technology-based coupled oscillators, which provide improvements of up to 3.5?increase in clock speed and up to 10.75?and 14.12?reduction in area and power consumption, respectively, as compared to a conventional Boolean CMOS accelerator executing the same functions.

Original languageEnglish (US)
Article number1
JournalACM Journal on Emerging Technologies in Computing Systems
Volume14
Issue number1
DOIs
StatePublished - Sep 2017

    Fingerprint

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this