An accurate lifetime analysis methodology incorporating governing NBTI mechanisms in high-k/SiO2 gate stacks

A. Neugroschel, G. Bersuker, R. Choi, C. Cochrane, Patrick M. Lenahan, D. Heh, C. Young, C. Y. Kang, B. H. Lee, R. Jammy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

30 Citations (Scopus)

Abstract

Extraction of the intrinsic NBTI degradation rate in the high-k pMOSFETs was found to require correction of the measured threshold voltage shift (ΔVTH) for the fast transient charging contribution caused by the charge trapping in pre-existing defects in high-k films. The proposed analysis methodology leads to a significantly lower estimated lifetime than that obtained by the generally used approach. It was determined that the interface state generation process contains a fast component most likely associated with the defects in the SiO2 interfacial layer induced by the overlaying high-k film. An intrinsic interface state generation rate obtained by subtracting the fast trapping component is found to be similar to that of the conventional SiO2 dielectric.

Original languageEnglish (US)
Title of host publication2006 International Electron Devices Meeting Technical Digest, IEDM
DOIs
StatePublished - Dec 1 2006
Event2006 International Electron Devices Meeting, IEDM - San Francisco, CA, United States
Duration: Dec 10 2006Dec 13 2006

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)0163-1918

Other

Other2006 International Electron Devices Meeting, IEDM
CountryUnited States
CitySan Francisco, CA
Period12/10/0612/13/06

Fingerprint

Interface states
trapping
methodology
life (durability)
Charge trapping
Defects
defects
Threshold voltage
threshold voltage
charging
degradation
Degradation
shift
4-nitrobenzylthioinosine
Negative bias temperature instability

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

Cite this

Neugroschel, A., Bersuker, G., Choi, R., Cochrane, C., Lenahan, P. M., Heh, D., ... Jammy, R. (2006). An accurate lifetime analysis methodology incorporating governing NBTI mechanisms in high-k/SiO2 gate stacks. In 2006 International Electron Devices Meeting Technical Digest, IEDM [4154191] (Technical Digest - International Electron Devices Meeting, IEDM). https://doi.org/10.1109/IEDM.2006.346772
Neugroschel, A. ; Bersuker, G. ; Choi, R. ; Cochrane, C. ; Lenahan, Patrick M. ; Heh, D. ; Young, C. ; Kang, C. Y. ; Lee, B. H. ; Jammy, R. / An accurate lifetime analysis methodology incorporating governing NBTI mechanisms in high-k/SiO2 gate stacks. 2006 International Electron Devices Meeting Technical Digest, IEDM. 2006. (Technical Digest - International Electron Devices Meeting, IEDM).
@inproceedings{a30a1145d3744401940bf45c88c9fe43,
title = "An accurate lifetime analysis methodology incorporating governing NBTI mechanisms in high-k/SiO2 gate stacks",
abstract = "Extraction of the intrinsic NBTI degradation rate in the high-k pMOSFETs was found to require correction of the measured threshold voltage shift (ΔVTH) for the fast transient charging contribution caused by the charge trapping in pre-existing defects in high-k films. The proposed analysis methodology leads to a significantly lower estimated lifetime than that obtained by the generally used approach. It was determined that the interface state generation process contains a fast component most likely associated with the defects in the SiO2 interfacial layer induced by the overlaying high-k film. An intrinsic interface state generation rate obtained by subtracting the fast trapping component is found to be similar to that of the conventional SiO2 dielectric.",
author = "A. Neugroschel and G. Bersuker and R. Choi and C. Cochrane and Lenahan, {Patrick M.} and D. Heh and C. Young and Kang, {C. Y.} and Lee, {B. H.} and R. Jammy",
year = "2006",
month = "12",
day = "1",
doi = "10.1109/IEDM.2006.346772",
language = "English (US)",
isbn = "1424404398",
series = "Technical Digest - International Electron Devices Meeting, IEDM",
booktitle = "2006 International Electron Devices Meeting Technical Digest, IEDM",

}

Neugroschel, A, Bersuker, G, Choi, R, Cochrane, C, Lenahan, PM, Heh, D, Young, C, Kang, CY, Lee, BH & Jammy, R 2006, An accurate lifetime analysis methodology incorporating governing NBTI mechanisms in high-k/SiO2 gate stacks. in 2006 International Electron Devices Meeting Technical Digest, IEDM., 4154191, Technical Digest - International Electron Devices Meeting, IEDM, 2006 International Electron Devices Meeting, IEDM, San Francisco, CA, United States, 12/10/06. https://doi.org/10.1109/IEDM.2006.346772

An accurate lifetime analysis methodology incorporating governing NBTI mechanisms in high-k/SiO2 gate stacks. / Neugroschel, A.; Bersuker, G.; Choi, R.; Cochrane, C.; Lenahan, Patrick M.; Heh, D.; Young, C.; Kang, C. Y.; Lee, B. H.; Jammy, R.

2006 International Electron Devices Meeting Technical Digest, IEDM. 2006. 4154191 (Technical Digest - International Electron Devices Meeting, IEDM).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - An accurate lifetime analysis methodology incorporating governing NBTI mechanisms in high-k/SiO2 gate stacks

AU - Neugroschel, A.

AU - Bersuker, G.

AU - Choi, R.

AU - Cochrane, C.

AU - Lenahan, Patrick M.

AU - Heh, D.

AU - Young, C.

AU - Kang, C. Y.

AU - Lee, B. H.

AU - Jammy, R.

PY - 2006/12/1

Y1 - 2006/12/1

N2 - Extraction of the intrinsic NBTI degradation rate in the high-k pMOSFETs was found to require correction of the measured threshold voltage shift (ΔVTH) for the fast transient charging contribution caused by the charge trapping in pre-existing defects in high-k films. The proposed analysis methodology leads to a significantly lower estimated lifetime than that obtained by the generally used approach. It was determined that the interface state generation process contains a fast component most likely associated with the defects in the SiO2 interfacial layer induced by the overlaying high-k film. An intrinsic interface state generation rate obtained by subtracting the fast trapping component is found to be similar to that of the conventional SiO2 dielectric.

AB - Extraction of the intrinsic NBTI degradation rate in the high-k pMOSFETs was found to require correction of the measured threshold voltage shift (ΔVTH) for the fast transient charging contribution caused by the charge trapping in pre-existing defects in high-k films. The proposed analysis methodology leads to a significantly lower estimated lifetime than that obtained by the generally used approach. It was determined that the interface state generation process contains a fast component most likely associated with the defects in the SiO2 interfacial layer induced by the overlaying high-k film. An intrinsic interface state generation rate obtained by subtracting the fast trapping component is found to be similar to that of the conventional SiO2 dielectric.

UR - http://www.scopus.com/inward/record.url?scp=46049085849&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=46049085849&partnerID=8YFLogxK

U2 - 10.1109/IEDM.2006.346772

DO - 10.1109/IEDM.2006.346772

M3 - Conference contribution

AN - SCOPUS:46049085849

SN - 1424404398

SN - 9781424404391

T3 - Technical Digest - International Electron Devices Meeting, IEDM

BT - 2006 International Electron Devices Meeting Technical Digest, IEDM

ER -

Neugroschel A, Bersuker G, Choi R, Cochrane C, Lenahan PM, Heh D et al. An accurate lifetime analysis methodology incorporating governing NBTI mechanisms in high-k/SiO2 gate stacks. In 2006 International Electron Devices Meeting Technical Digest, IEDM. 2006. 4154191. (Technical Digest - International Electron Devices Meeting, IEDM). https://doi.org/10.1109/IEDM.2006.346772