An accurate lifetime analysis methodology incorporating governing NBTI mechanisms in high-k/SiO2 gate stacks

A. Neugroschel, G. Bersuker, R. Choi, C. Cochrane, P. Lenahan, D. Heh, C. Young, C. Y. Kang, B. H. Lee, R. Jammy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

29 Scopus citations

Abstract

Extraction of the intrinsic NBTI degradation rate in the high-k pMOSFETs was found to require correction of the measured threshold voltage shift (ΔVTH) for the fast transient charging contribution caused by the charge trapping in pre-existing defects in high-k films. The proposed analysis methodology leads to a significantly lower estimated lifetime than that obtained by the generally used approach. It was determined that the interface state generation process contains a fast component most likely associated with the defects in the SiO2 interfacial layer induced by the overlaying high-k film. An intrinsic interface state generation rate obtained by subtracting the fast trapping component is found to be similar to that of the conventional SiO2 dielectric.

Original languageEnglish (US)
Title of host publication2006 International Electron Devices Meeting Technical Digest, IEDM
DOIs
StatePublished - Dec 1 2006
Event2006 International Electron Devices Meeting, IEDM - San Francisco, CA, United States
Duration: Dec 10 2006Dec 13 2006

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)0163-1918

Other

Other2006 International Electron Devices Meeting, IEDM
CountryUnited States
CitySan Francisco, CA
Period12/10/0612/13/06

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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    Neugroschel, A., Bersuker, G., Choi, R., Cochrane, C., Lenahan, P., Heh, D., Young, C., Kang, C. Y., Lee, B. H., & Jammy, R. (2006). An accurate lifetime analysis methodology incorporating governing NBTI mechanisms in high-k/SiO2 gate stacks. In 2006 International Electron Devices Meeting Technical Digest, IEDM [4154191] (Technical Digest - International Electron Devices Meeting, IEDM). https://doi.org/10.1109/IEDM.2006.346772