A critical component of a real-time operating system (RTOS) is its process scheduler. While the prior research on process scheduling focuses mostly on meeting hard/soft deadlines, preemption and priory assignment related issues, problems arise from existence of cache memories are largely ignored. Focusing on data accesses and a cache based embedded system, this paper proposes an adaptive locality-conscious process scheduling algorithm. The main goal of the proposed algorithm is to exploit (reuse) the contents of the on-chip cache memory to the highest extent possible. The algorithm tries to achieve its goal by determining the order in which the processes get scheduled such that the successively-executing processes share a large number of data elements. We implemented our scheduler within a customized simulation platform and simulated it using a set of benchmark codes. Our experimental results reveal that the proposed scheduling algorithm is very successful in practice, and reduces process completion times significantly for both rate-monotonic scheduling (RMS) and earliest-deadline-first scheduling (EDF). We also explain how process code transformations can be used for increasing the savings achieved by the locality-conscious scheduler, and show how the proposed approach operates with a base scheduler such as RMS and EDF.
|Original language||English (US)|
|Number of pages||11|
|Journal||Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS|
|State||Published - Sep 26 2005|
|Event||11th IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2005 - San Francisco, CA, United States|
Duration: Mar 7 2005 → Mar 10 2005
All Science Journal Classification (ASJC) codes