@inproceedings{87ccd3cdfb0b4fcdad2b8f5cb3c62aa2,
title = "An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires",
abstract = "An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires is proposed. Among emerging CMOS devices, nanowire (NW) / gate-all-around (GAA) silicon MOSFETs have shown advantages for scaling features as the semiconductor technology continues to progress. While preserving the intrinsic GAA advantages, this paper provides a design methodology for the optimal and feasible manufacturability with different doping concentrations to achieve high density design and assesses the performance via three-dimensional TCAD simulation. However, due to limited atoms in the extremely scaled channel, a heavy doping with in-situ doping process is needed. In addition, using vertical stacked gate-all-around MOSFETs to achieve high density in the same layout area with the proposed multi-threshold doping scheme is beneficial for system on chip (SoC) application. Circuit performance projection of the 6-T SRAM is provided based on balanced read and write performances.",
author = "Huang, {Ya Chi} and Chiang, {Meng Hsueh} and Wang, {Shui Jinn} and Gupta, {Sumeet Kumar}",
year = "2018",
month = jun,
day = "27",
doi = "10.1109/ICICDT.2018.8399770",
language = "English (US)",
series = "ICICDT 2018 - International Conference on IC Design and Technology, Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "117--120",
booktitle = "ICICDT 2018 - International Conference on IC Design and Technology, Proceedings",
address = "United States",
note = "2018 International Conference on IC Design and Technology, ICICDT 2018 ; Conference date: 04-06-2018 Through 06-06-2018",
}