An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires

Ya Chi Huang; Meng Hsueh Chiang; Shui Jinn Wang; Sumeet Kumar Gupta

doi:10.1109/ICICDT.2018.8399770

An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires

Ya Chi Huang, Meng Hsueh Chiang, Shui Jinn Wang, Sumeet Kumar Gupta

Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Scopus citations

Abstract

An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires is proposed. Among emerging CMOS devices, nanowire (NW) / gate-all-around (GAA) silicon MOSFETs have shown advantages for scaling features as the semiconductor technology continues to progress. While preserving the intrinsic GAA advantages, this paper provides a design methodology for the optimal and feasible manufacturability with different doping concentrations to achieve high density design and assesses the performance via three-dimensional TCAD simulation. However, due to limited atoms in the extremely scaled channel, a heavy doping with in-situ doping process is needed. In addition, using vertical stacked gate-all-around MOSFETs to achieve high density in the same layout area with the proposed multi-threshold doping scheme is beneficial for system on chip (SoC) application. Circuit performance projection of the 6-T SRAM is provided based on balanced read and write performances.

Original language	English (US)
Title of host publication	ICICDT 2018 - International Conference on IC Design and Technology, Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	117-120
Number of pages	4
ISBN (Electronic)	9781538625491
DOIs	https://doi.org/10.1109/ICICDT.2018.8399770
State	Published - Jun 27 2018
Event	2018 International Conference on IC Design and Technology, ICICDT 2018 - Otranto, Italy Duration: Jun 4 2018 → Jun 6 2018

Publication series

Name	ICICDT 2018 - International Conference on IC Design and Technology, Proceedings

Other

Other	2018 International Conference on IC Design and Technology, ICICDT 2018
Country/Territory	Italy
City	Otranto
Period	6/4/18 → 6/6/18

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality

Access to Document

10.1109/ICICDT.2018.8399770

Cite this

Huang, Y. C., Chiang, M. H., Wang, S. J., & Gupta, S. K. (2018). An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires. In ICICDT 2018 - International Conference on IC Design and Technology, Proceedings (pp. 117-120). (ICICDT 2018 - International Conference on IC Design and Technology, Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICICDT.2018.8399770

Huang, Ya Chi ; Chiang, Meng Hsueh ; Wang, Shui Jinn ; Gupta, Sumeet Kumar. / An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires. ICICDT 2018 - International Conference on IC Design and Technology, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 117-120 (ICICDT 2018 - International Conference on IC Design and Technology, Proceedings).

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title = "An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires",

abstract = "An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires is proposed. Among emerging CMOS devices, nanowire (NW) / gate-all-around (GAA) silicon MOSFETs have shown advantages for scaling features as the semiconductor technology continues to progress. While preserving the intrinsic GAA advantages, this paper provides a design methodology for the optimal and feasible manufacturability with different doping concentrations to achieve high density design and assesses the performance via three-dimensional TCAD simulation. However, due to limited atoms in the extremely scaled channel, a heavy doping with in-situ doping process is needed. In addition, using vertical stacked gate-all-around MOSFETs to achieve high density in the same layout area with the proposed multi-threshold doping scheme is beneficial for system on chip (SoC) application. Circuit performance projection of the 6-T SRAM is provided based on balanced read and write performances.",

author = "Huang, {Ya Chi} and Chiang, {Meng Hsueh} and Wang, {Shui Jinn} and Gupta, {Sumeet Kumar}",

note = "Funding Information: Acknowledgment: This work was supported in part by the Ministry of Science and Technology of Taiwan. The authors would like to thank the National Center for High-Performance Computing, National Chip Implementation Center, and Nano Device Laboratories for technical support. Publisher Copyright: {\textcopyright} 2018 IEEE.; 2018 International Conference on IC Design and Technology, ICICDT 2018 ; Conference date: 04-06-2018 Through 06-06-2018",

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doi = "10.1109/ICICDT.2018.8399770",

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Huang, YC, Chiang, MH, Wang, SJ & Gupta, SK 2018, An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires. in ICICDT 2018 - International Conference on IC Design and Technology, Proceedings. ICICDT 2018 - International Conference on IC Design and Technology, Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 117-120, 2018 International Conference on IC Design and Technology, ICICDT 2018, Otranto, Italy, 6/4/18. https://doi.org/10.1109/ICICDT.2018.8399770

An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires. / Huang, Ya Chi; Chiang, Meng Hsueh; Wang, Shui Jinn; Gupta, Sumeet Kumar.

ICICDT 2018 - International Conference on IC Design and Technology, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. p. 117-120 (ICICDT 2018 - International Conference on IC Design and Technology, Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Gupta, Sumeet Kumar

N1 - Funding Information: Acknowledgment: This work was supported in part by the Ministry of Science and Technology of Taiwan. The authors would like to thank the National Center for High-Performance Computing, National Chip Implementation Center, and Nano Device Laboratories for technical support. Publisher Copyright: © 2018 IEEE.

PY - 2018/6/27

Y1 - 2018/6/27

N2 - An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires is proposed. Among emerging CMOS devices, nanowire (NW) / gate-all-around (GAA) silicon MOSFETs have shown advantages for scaling features as the semiconductor technology continues to progress. While preserving the intrinsic GAA advantages, this paper provides a design methodology for the optimal and feasible manufacturability with different doping concentrations to achieve high density design and assesses the performance via three-dimensional TCAD simulation. However, due to limited atoms in the extremely scaled channel, a heavy doping with in-situ doping process is needed. In addition, using vertical stacked gate-all-around MOSFETs to achieve high density in the same layout area with the proposed multi-threshold doping scheme is beneficial for system on chip (SoC) application. Circuit performance projection of the 6-T SRAM is provided based on balanced read and write performances.

AB - An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires is proposed. Among emerging CMOS devices, nanowire (NW) / gate-all-around (GAA) silicon MOSFETs have shown advantages for scaling features as the semiconductor technology continues to progress. While preserving the intrinsic GAA advantages, this paper provides a design methodology for the optimal and feasible manufacturability with different doping concentrations to achieve high density design and assesses the performance via three-dimensional TCAD simulation. However, due to limited atoms in the extremely scaled channel, a heavy doping with in-situ doping process is needed. In addition, using vertical stacked gate-all-around MOSFETs to achieve high density in the same layout area with the proposed multi-threshold doping scheme is beneficial for system on chip (SoC) application. Circuit performance projection of the 6-T SRAM is provided based on balanced read and write performances.

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Huang YC, Chiang MH, Wang SJ, Gupta SK. An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires. In ICICDT 2018 - International Conference on IC Design and Technology, Proceedings. Institute of Electrical and Electronics Engineers Inc. 2018. p. 117-120. (ICICDT 2018 - International Conference on IC Design and Technology, Proceedings). https://doi.org/10.1109/ICICDT.2018.8399770

An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires

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