An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires

Ya Chi Huang, Meng Hsueh Chiang, Shui Jinn Wang, Sumeet Kumar Gupta

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires is proposed. Among emerging CMOS devices, nanowire (NW) / gate-all-around (GAA) silicon MOSFETs have shown advantages for scaling features as the semiconductor technology continues to progress. While preserving the intrinsic GAA advantages, this paper provides a design methodology for the optimal and feasible manufacturability with different doping concentrations to achieve high density design and assesses the performance via three-dimensional TCAD simulation. However, due to limited atoms in the extremely scaled channel, a heavy doping with in-situ doping process is needed. In addition, using vertical stacked gate-all-around MOSFETs to achieve high density in the same layout area with the proposed multi-threshold doping scheme is beneficial for system on chip (SoC) application. Circuit performance projection of the 6-T SRAM is provided based on balanced read and write performances.

Original languageEnglish (US)
Title of host publicationICICDT 2018 - International Conference on IC Design and Technology, Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages117-120
Number of pages4
ISBN (Electronic)9781538625491
DOIs
StatePublished - Jun 27 2018
Event2018 International Conference on IC Design and Technology, ICICDT 2018 - Otranto, Italy
Duration: Jun 4 2018Jun 6 2018

Publication series

NameICICDT 2018 - International Conference on IC Design and Technology, Proceedings

Other

Other2018 International Conference on IC Design and Technology, ICICDT 2018
CountryItaly
CityOtranto
Period6/4/186/6/18

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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  • Cite this

    Huang, Y. C., Chiang, M. H., Wang, S. J., & Gupta, S. K. (2018). An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires. In ICICDT 2018 - International Conference on IC Design and Technology, Proceedings (pp. 117-120). (ICICDT 2018 - International Conference on IC Design and Technology, Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICICDT.2018.8399770