Abstract
An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires is proposed. Among emerging CMOS devices, nanowire (NW) / gate-all-around (GAA) silicon MOSFETs have shown advantages for scaling features as the semiconductor technology continues to progress. While preserving the intrinsic GAA advantages, this paper provides a design methodology for the optimal and feasible manufacturability with different doping concentrations to achieve high density design and assesses the performance via three-dimensional TCAD simulation. However, due to limited atoms in the extremely scaled channel, a heavy doping with in-situ doping process is needed. In addition, using vertical stacked gate-all-around MOSFETs to achieve high density in the same layout area with the proposed multi-threshold doping scheme is beneficial for system on chip (SoC) application. Circuit performance projection of the 6-T SRAM is provided based on balanced read and write performances.
| Original language | English (US) |
|---|---|
| Title of host publication | ICICDT 2018 - International Conference on IC Design and Technology, Proceedings |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 117-120 |
| Number of pages | 4 |
| ISBN (Electronic) | 9781538625491 |
| DOIs | |
| State | Published - Jun 27 2018 |
| Event | 2018 International Conference on IC Design and Technology, ICICDT 2018 - Otranto, Italy Duration: Jun 4 2018 → Jun 6 2018 |
Publication series
| Name | ICICDT 2018 - International Conference on IC Design and Technology, Proceedings |
|---|
Other
| Other | 2018 International Conference on IC Design and Technology, ICICDT 2018 |
|---|---|
| Country | Italy |
| City | Otranto |
| Period | 6/4/18 → 6/6/18 |
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All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
- Safety, Risk, Reliability and Quality
Cite this
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An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires. / Huang, Ya Chi; Chiang, Meng Hsueh; Wang, Shui Jinn; Gupta, Sumeet Kumar.
ICICDT 2018 - International Conference on IC Design and Technology, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. p. 117-120 (ICICDT 2018 - International Conference on IC Design and Technology, Proceedings).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires
AU - Huang, Ya Chi
AU - Chiang, Meng Hsueh
AU - Wang, Shui Jinn
AU - Gupta, Sumeet Kumar
PY - 2018/6/27
Y1 - 2018/6/27
N2 - An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires is proposed. Among emerging CMOS devices, nanowire (NW) / gate-all-around (GAA) silicon MOSFETs have shown advantages for scaling features as the semiconductor technology continues to progress. While preserving the intrinsic GAA advantages, this paper provides a design methodology for the optimal and feasible manufacturability with different doping concentrations to achieve high density design and assesses the performance via three-dimensional TCAD simulation. However, due to limited atoms in the extremely scaled channel, a heavy doping with in-situ doping process is needed. In addition, using vertical stacked gate-all-around MOSFETs to achieve high density in the same layout area with the proposed multi-threshold doping scheme is beneficial for system on chip (SoC) application. Circuit performance projection of the 6-T SRAM is provided based on balanced read and write performances.
AB - An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires is proposed. Among emerging CMOS devices, nanowire (NW) / gate-all-around (GAA) silicon MOSFETs have shown advantages for scaling features as the semiconductor technology continues to progress. While preserving the intrinsic GAA advantages, this paper provides a design methodology for the optimal and feasible manufacturability with different doping concentrations to achieve high density design and assesses the performance via three-dimensional TCAD simulation. However, due to limited atoms in the extremely scaled channel, a heavy doping with in-situ doping process is needed. In addition, using vertical stacked gate-all-around MOSFETs to achieve high density in the same layout area with the proposed multi-threshold doping scheme is beneficial for system on chip (SoC) application. Circuit performance projection of the 6-T SRAM is provided based on balanced read and write performances.
UR - http://www.scopus.com/inward/record.url?scp=85050298395&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85050298395&partnerID=8YFLogxK
U2 - 10.1109/ICICDT.2018.8399770
DO - 10.1109/ICICDT.2018.8399770
M3 - Conference contribution
AN - SCOPUS:85050298395
T3 - ICICDT 2018 - International Conference on IC Design and Technology, Proceedings
SP - 117
EP - 120
BT - ICICDT 2018 - International Conference on IC Design and Technology, Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
ER -