An energy saving strategy based on adaptive loop parallelization

I. Kadayif, M. Kandemir, M. Karakoy

Research output: Contribution to journalArticle

18 Scopus citations

Abstract

In this paper, we evaluate an adaptive loop parallelization strategy (i.e., a strategy that allows each loop nest to execute using different number of processors if doing so is beneficial) and measure the potential energy savings when unused processors during execution of a nested loop in a multi-processor on-a-chip (MPoC) are shut down (i.e., placed into a power-down or sleep state). Our results show that shutting down unused processors can lead to as much as 67% energy savings with up to 17% performance loss in a set of array-intensive applications. We also discuss and evaluate a processor pre-activation strategy based on compile-time analysis of nested loops. Based on our experiments, we conclude that an adaptive loop parallelization strategy combined with idle processor shut-down and pre-activation can be very effective in reducing energy consumption without increasing execution time.

Original languageEnglish (US)
Pages (from-to)195-200
Number of pages6
JournalProceedings - Design Automation Conference
DOIs
StatePublished - Jan 1 2002

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering

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