An evaluation of selective depipelining for FPGA-based energy-reducing irregular code coprocessors

John Morgan Sampson, Manish Arora, Nathan Goulding-Hotta, Ganesh Venkatesh, Jonathan Babb, Vikram Bhatt, Steven Swanson, Michael Bedford Taylor

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

As the complexity of FPGA-based systems scales, the importance of efficiently handling irregular code increases. Recent work has proposed Irregular Code Energy Reducers (ICERs), a high-level synthesis approach for FPGAs that offers significant energy reduction for irregular code compared to a soft core processor. ICERs target the hot-spots of programs, and are seamlessly connected via a shared L1 cache with a soft processor that executes the cold code. This paper evaluates the application of the selective depipelining (SDP) technique to ICERs, which greatly reduces both the execution time and energy of irregular computations. SDP enables irregular computations to be expressed as large, fast, low-power combinational blocks. SDP maintains high memory bandwidth by scheduling the many potentially dependent memory operations within these blocks onto a high-frequency, highly-multiplexed coherent memory while scheduling combinational operations at a much lower frequency. SDP is a key enabler for improving the execution properties of irregular computations that are difficult to parallelize. We show that applying SDP to ICERs reduces energy-delay by 2.62× relative to ICERs. ICERs with SDP are up to 2.38× faster than a soft core processor and reduce energy consumption by up to 15.83× for a variety of irregular applications.

Original languageEnglish (US)
Title of host publicationProceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011
Pages24-29
Number of pages6
DOIs
StatePublished - Nov 9 2011
Event21st International Conference on Field Programmable Logic and Applications, FPL 2011 - Chania, Greece
Duration: Sep 5 2011Sep 7 2011

Publication series

NameProceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011

Other

Other21st International Conference on Field Programmable Logic and Applications, FPL 2011
CountryGreece
CityChania
Period9/5/119/7/11

Fingerprint

Field programmable gate arrays (FPGA)
Data storage equipment
Scheduling
Energy utilization
Bandwidth
Coprocessor
High level synthesis

All Science Journal Classification (ASJC) codes

  • Computer Science Applications

Cite this

Sampson, J. M., Arora, M., Goulding-Hotta, N., Venkatesh, G., Babb, J., Bhatt, V., ... Taylor, M. B. (2011). An evaluation of selective depipelining for FPGA-based energy-reducing irregular code coprocessors. In Proceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011 (pp. 24-29). [6044779] (Proceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011). https://doi.org/10.1109/FPL.2011.16
Sampson, John Morgan ; Arora, Manish ; Goulding-Hotta, Nathan ; Venkatesh, Ganesh ; Babb, Jonathan ; Bhatt, Vikram ; Swanson, Steven ; Taylor, Michael Bedford. / An evaluation of selective depipelining for FPGA-based energy-reducing irregular code coprocessors. Proceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011. 2011. pp. 24-29 (Proceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011).
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abstract = "As the complexity of FPGA-based systems scales, the importance of efficiently handling irregular code increases. Recent work has proposed Irregular Code Energy Reducers (ICERs), a high-level synthesis approach for FPGAs that offers significant energy reduction for irregular code compared to a soft core processor. ICERs target the hot-spots of programs, and are seamlessly connected via a shared L1 cache with a soft processor that executes the cold code. This paper evaluates the application of the selective depipelining (SDP) technique to ICERs, which greatly reduces both the execution time and energy of irregular computations. SDP enables irregular computations to be expressed as large, fast, low-power combinational blocks. SDP maintains high memory bandwidth by scheduling the many potentially dependent memory operations within these blocks onto a high-frequency, highly-multiplexed coherent memory while scheduling combinational operations at a much lower frequency. SDP is a key enabler for improving the execution properties of irregular computations that are difficult to parallelize. We show that applying SDP to ICERs reduces energy-delay by 2.62× relative to ICERs. ICERs with SDP are up to 2.38× faster than a soft core processor and reduce energy consumption by up to 15.83× for a variety of irregular applications.",
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Sampson, JM, Arora, M, Goulding-Hotta, N, Venkatesh, G, Babb, J, Bhatt, V, Swanson, S & Taylor, MB 2011, An evaluation of selective depipelining for FPGA-based energy-reducing irregular code coprocessors. in Proceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011., 6044779, Proceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011, pp. 24-29, 21st International Conference on Field Programmable Logic and Applications, FPL 2011, Chania, Greece, 9/5/11. https://doi.org/10.1109/FPL.2011.16

An evaluation of selective depipelining for FPGA-based energy-reducing irregular code coprocessors. / Sampson, John Morgan; Arora, Manish; Goulding-Hotta, Nathan; Venkatesh, Ganesh; Babb, Jonathan; Bhatt, Vikram; Swanson, Steven; Taylor, Michael Bedford.

Proceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011. 2011. p. 24-29 6044779 (Proceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Sampson JM, Arora M, Goulding-Hotta N, Venkatesh G, Babb J, Bhatt V et al. An evaluation of selective depipelining for FPGA-based energy-reducing irregular code coprocessors. In Proceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011. 2011. p. 24-29. 6044779. (Proceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011). https://doi.org/10.1109/FPL.2011.16