An examination of the architecture and system-level tradeoffs of employing steep slope devices in 3D CMPs

Karthik Swaminathan, Huichu Liu, Jack Sampson, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Scopus citations

Abstract

For any given application, there is an optimal throughput point in the space of per-processor performance and the number of such processors given to that application. However, due to thermal, yield, and other constraints, not all of these optimal points can plausibly be constructed with a given technology. In this paper, we look at how emerging steep slope devices, 3D circuit integration, and trends in process technology scaling will combine to shift the boundaries of both attainable performance, and the optimal set of technologies to employ to achieve it. We propose a heterogeneous-technology 3D architecture capable of operating efficiently at an expanded number of points in this larger design space and devise a heterogeneity and thermal aware scheduling algorithm to exploit its potential. Our heterogeneous mapping techniques are capable of producing speedups ranging from 17% for a high end server workloads running at around 90°C to over 160% for embedded systems running below 60°C.

Original languageEnglish (US)
Title of host publication41st Annual International Symposium on Computer Architecture, ISCA 2014 - Conference Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages241-252
Number of pages12
ISBN (Print)9781479943968
DOIs
StatePublished - Jan 1 2014
Event2014 ACM/IEEE 41st International Symposium on Computer Architecture, ISCA 2014 - Minneapolis, MN, United States
Duration: Jun 14 2014Jun 18 2014

Publication series

NameProceedings - International Symposium on Computer Architecture
ISSN (Print)1063-6897

Other

Other2014 ACM/IEEE 41st International Symposium on Computer Architecture, ISCA 2014
CountryUnited States
CityMinneapolis, MN
Period6/14/146/18/14

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

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    Swaminathan, K., Liu, H., Sampson, J., & Narayanan, V. (2014). An examination of the architecture and system-level tradeoffs of employing steep slope devices in 3D CMPs. In 41st Annual International Symposium on Computer Architecture, ISCA 2014 - Conference Proceedings (pp. 241-252). [6853197] (Proceedings - International Symposium on Computer Architecture). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCA.2014.6853197