An FPGA implementation of resource-optimized dynamic digital beamformer for a portable ultrasound imaging system

Jingwei Xu, Yi Zheng, Mohan Chirala, Mohamed Khaled Almekkawy

Research output: Contribution to journalArticle

Abstract

This paper presents a resource-friendly dynamic digital beamformer for a portable ultrasound imaging system based on a single field-programmable gate array (FPGA). The core of the ultrasound imaging system is a 128-channel receive beamformer with fully dynamic focusing embedded in a single FPGA chip, which operates at a frequency of 40 MHz. The Rx beamformer is composed of a midend processing module, a backend processing module, and a control block. The midend processing module is established using the implementation of the delay summation through coarse delays and fine delays, with which delays could vary continuously to support dynamic beamforming. In order to enhance spatial and contrast resolution, the Rx beamformer is further accommodated by employing a polyphase filter, which improves the effective beamforming frequency to 240 MHz. The control block generates control signals based on a memory management block, which doubles the data transfer rate. The processed data is wirelessly sent to a commercial Android device. The low cost ultrasound imaging system supports real-time images with a frame rate of 40 fps, due to the limitation imposed by the wireless backhaul process. To reduce power consumption, a dynamic power management technique is used, with which the power consumption is reduced by 25%. This paper demonstrates the feasibility of the implementation of a high performance power-efficient dynamic beamformer in a single FPGA-based portable ultrasound system.

Original languageEnglish (US)
Pages (from-to)59-71
Number of pages13
JournalAdvances in Science, Technology and Engineering Systems
Volume3
Issue number4
DOIs
StatePublished - Jan 1 2018

Fingerprint

field-programmable gate arrays
Imaging systems
Field programmable gate arrays (FPGA)
resources
Ultrasonics
modules
beamforming
Beamforming
Electric power utilization
Processing
Data transfer rates
support systems
spatial resolution
chips
Resources
Ultrasound
Imaging
filters
Data storage equipment
Module

All Science Journal Classification (ASJC) codes

  • Engineering (miscellaneous)
  • Physics and Astronomy (miscellaneous)
  • Management of Technology and Innovation

Cite this

@article{581bf9a932014811908e735d1b5ba9bc,
title = "An FPGA implementation of resource-optimized dynamic digital beamformer for a portable ultrasound imaging system",
abstract = "This paper presents a resource-friendly dynamic digital beamformer for a portable ultrasound imaging system based on a single field-programmable gate array (FPGA). The core of the ultrasound imaging system is a 128-channel receive beamformer with fully dynamic focusing embedded in a single FPGA chip, which operates at a frequency of 40 MHz. The Rx beamformer is composed of a midend processing module, a backend processing module, and a control block. The midend processing module is established using the implementation of the delay summation through coarse delays and fine delays, with which delays could vary continuously to support dynamic beamforming. In order to enhance spatial and contrast resolution, the Rx beamformer is further accommodated by employing a polyphase filter, which improves the effective beamforming frequency to 240 MHz. The control block generates control signals based on a memory management block, which doubles the data transfer rate. The processed data is wirelessly sent to a commercial Android device. The low cost ultrasound imaging system supports real-time images with a frame rate of 40 fps, due to the limitation imposed by the wireless backhaul process. To reduce power consumption, a dynamic power management technique is used, with which the power consumption is reduced by 25{\%}. This paper demonstrates the feasibility of the implementation of a high performance power-efficient dynamic beamformer in a single FPGA-based portable ultrasound system.",
author = "Jingwei Xu and Yi Zheng and Mohan Chirala and Almekkawy, {Mohamed Khaled}",
year = "2018",
month = "1",
day = "1",
doi = "10.25046/aj030408",
language = "English (US)",
volume = "3",
pages = "59--71",
journal = "Advances in Science, Technology and Engineering Systems",
issn = "2415-6698",
publisher = "ASTES Publishers",
number = "4",

}

An FPGA implementation of resource-optimized dynamic digital beamformer for a portable ultrasound imaging system. / Xu, Jingwei; Zheng, Yi; Chirala, Mohan; Almekkawy, Mohamed Khaled.

In: Advances in Science, Technology and Engineering Systems, Vol. 3, No. 4, 01.01.2018, p. 59-71.

Research output: Contribution to journalArticle

TY - JOUR

T1 - An FPGA implementation of resource-optimized dynamic digital beamformer for a portable ultrasound imaging system

AU - Xu, Jingwei

AU - Zheng, Yi

AU - Chirala, Mohan

AU - Almekkawy, Mohamed Khaled

PY - 2018/1/1

Y1 - 2018/1/1

N2 - This paper presents a resource-friendly dynamic digital beamformer for a portable ultrasound imaging system based on a single field-programmable gate array (FPGA). The core of the ultrasound imaging system is a 128-channel receive beamformer with fully dynamic focusing embedded in a single FPGA chip, which operates at a frequency of 40 MHz. The Rx beamformer is composed of a midend processing module, a backend processing module, and a control block. The midend processing module is established using the implementation of the delay summation through coarse delays and fine delays, with which delays could vary continuously to support dynamic beamforming. In order to enhance spatial and contrast resolution, the Rx beamformer is further accommodated by employing a polyphase filter, which improves the effective beamforming frequency to 240 MHz. The control block generates control signals based on a memory management block, which doubles the data transfer rate. The processed data is wirelessly sent to a commercial Android device. The low cost ultrasound imaging system supports real-time images with a frame rate of 40 fps, due to the limitation imposed by the wireless backhaul process. To reduce power consumption, a dynamic power management technique is used, with which the power consumption is reduced by 25%. This paper demonstrates the feasibility of the implementation of a high performance power-efficient dynamic beamformer in a single FPGA-based portable ultrasound system.

AB - This paper presents a resource-friendly dynamic digital beamformer for a portable ultrasound imaging system based on a single field-programmable gate array (FPGA). The core of the ultrasound imaging system is a 128-channel receive beamformer with fully dynamic focusing embedded in a single FPGA chip, which operates at a frequency of 40 MHz. The Rx beamformer is composed of a midend processing module, a backend processing module, and a control block. The midend processing module is established using the implementation of the delay summation through coarse delays and fine delays, with which delays could vary continuously to support dynamic beamforming. In order to enhance spatial and contrast resolution, the Rx beamformer is further accommodated by employing a polyphase filter, which improves the effective beamforming frequency to 240 MHz. The control block generates control signals based on a memory management block, which doubles the data transfer rate. The processed data is wirelessly sent to a commercial Android device. The low cost ultrasound imaging system supports real-time images with a frame rate of 40 fps, due to the limitation imposed by the wireless backhaul process. To reduce power consumption, a dynamic power management technique is used, with which the power consumption is reduced by 25%. This paper demonstrates the feasibility of the implementation of a high performance power-efficient dynamic beamformer in a single FPGA-based portable ultrasound system.

UR - http://www.scopus.com/inward/record.url?scp=85061841376&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85061841376&partnerID=8YFLogxK

U2 - 10.25046/aj030408

DO - 10.25046/aj030408

M3 - Article

VL - 3

SP - 59

EP - 71

JO - Advances in Science, Technology and Engineering Systems

JF - Advances in Science, Technology and Engineering Systems

SN - 2415-6698

IS - 4

ER -