An ILP based approach to address code generation for digital signal processors

O. Ozturk, M. Kandemir, S. Tosun

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

One of the most important problems in resource-constrained embedded systems is limited memory space for code and data. This paper targets at DSP based architectures and proposes an ILP (integer linear programming) based approach for reducing code memory space requirements by exploiting the auto-increment and auto-decrement addressing modes provided by DSPs. Specifically, we address the problem of effective use of address registers, demonstrate how we can take advantage of additional capabilities that exists in some recent DSPs (such as modify registers), and discuss how our ILP-based solution can be used for performing tradeoffs between code memory and data memory space requirements. We also compare our approach to a previously-proposed heuristic solution. Our experimental analysis using several applications indicate that the proposed ILP-based approach is very effective in reducing both code memory demand and execution cycles, and the solution times it takes are within tolerable limits.

Original languageEnglish (US)
Title of host publicationGLSVLSI'06 - Proceedings of the 2006 ACM Great Lakes Symposium on VLSI
PublisherAssociation for Computing Machinery
Pages37-42
Number of pages6
ISBN (Print)1595933476, 9781595933478
DOIs
StatePublished - 2006
EventGLSVLSI'06 - 2006 ACM Great Lakes Symposium on VLSI - Philadelphia, PA, United States
Duration: Apr 30 2006May 2 2006

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
Volume2006

Other

OtherGLSVLSI'06 - 2006 ACM Great Lakes Symposium on VLSI
CountryUnited States
CityPhiladelphia, PA
Period4/30/065/2/06

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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