TY - GEN
T1 - An in-depth study of next generation interface for emerging non-volatile memories
AU - Choi, Wonil
AU - Zhang, Jie
AU - Gao, Shuwen
AU - Lee, Jaesoo
AU - Jung, Myoungsoo
AU - Kandemir, Mahmut
N1 - Funding Information:
This research is supported in part by NRF grants 2016R1C1B2015312, 2015M3C4A7065645, and IITP grant, 2015-R0346-15-1008. This work is also supported in part by NSF grants 1213052, 1205618, 1302557, 1526750, 1409095, and 1439021. Mahmut Kandemir and Myoungsoo Jung are the co-corresponding authors.
Publisher Copyright:
© 2016 IEEE.
PY - 2016/8/17
Y1 - 2016/8/17
N2 - Non-Volatile Memory Express (NVMe) is designed with the goal of unlocking the potential of low-latency, randomaccess, memory-based storage devices. Specifically, NVMe employs various rich communication and queuing mechanism that can ideally schedule four billion I/O instructions for a single storage device. To explore NVMe with assorted user scenarios, we model diverse interface-level design parameters such as PCI Express, NVMe protocol, and different rich queuing mechanisms by considering a wide spectrum of host-level system configurations. In this work, we also assemble a comprehensive memory stack with different types of emerging NVM technologies, which can give us detailed NVMe related statistics like I/O request lifespans and I/O thread-related parallelism. Our evaluation results reveal that, i) while NVMe handshaking is light-weight for flash memory that uses block-based accesses (Block NVM), it can impose tremendous overheads for memristor technology (DRAM-like NVM), ii) in contrast to the common expectation, the performance of an NVMe-equipped system may not improve in a scalable fashion as the queue depth and the number of queues increase, and iii) more- and deeperqueue systems atop a Block NVM can significantly suffer from tremendous host-side memory requirements, whereas a DRAMlike NVM can cause frequent system stalls due to NVMe's inefficient interrupt service routine.
AB - Non-Volatile Memory Express (NVMe) is designed with the goal of unlocking the potential of low-latency, randomaccess, memory-based storage devices. Specifically, NVMe employs various rich communication and queuing mechanism that can ideally schedule four billion I/O instructions for a single storage device. To explore NVMe with assorted user scenarios, we model diverse interface-level design parameters such as PCI Express, NVMe protocol, and different rich queuing mechanisms by considering a wide spectrum of host-level system configurations. In this work, we also assemble a comprehensive memory stack with different types of emerging NVM technologies, which can give us detailed NVMe related statistics like I/O request lifespans and I/O thread-related parallelism. Our evaluation results reveal that, i) while NVMe handshaking is light-weight for flash memory that uses block-based accesses (Block NVM), it can impose tremendous overheads for memristor technology (DRAM-like NVM), ii) in contrast to the common expectation, the performance of an NVMe-equipped system may not improve in a scalable fashion as the queue depth and the number of queues increase, and iii) more- and deeperqueue systems atop a Block NVM can significantly suffer from tremendous host-side memory requirements, whereas a DRAMlike NVM can cause frequent system stalls due to NVMe's inefficient interrupt service routine.
UR - http://www.scopus.com/inward/record.url?scp=84986570785&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84986570785&partnerID=8YFLogxK
U2 - 10.1109/NVMSA.2016.7547177
DO - 10.1109/NVMSA.2016.7547177
M3 - Conference contribution
AN - SCOPUS:84986570785
T3 - 2016 5th Non-Volatile Memory Systems and Applications Symposium, NVMSA 2016
BT - 2016 5th Non-Volatile Memory Systems and Applications Symposium, NVMSA 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 5th Non-Volatile Memory Systems and Applications Symposium, NVMSA 2016
Y2 - 17 August 2016 through 19 August 2016
ER -