An integer linear programming based approach for parallelizing applications in on-chip multiprocessors

I. Kadayif, Mahmut Kandemir, U. Sezer

Research output: Contribution to journalArticle

41 Citations (Scopus)

Abstract

With energy consumption becoming one of the first-class optimization parameters in computer system design, compilation techniques that consider performance and energy simultaneously are expected to play a central role. In particular, compiling a given application code under performance and energy constraints is becoming an important problem. In this paper, we focus on an on-chip multiprocessor architecture and present a parallelization strategy based on integer linear programming. Given an array-intensive application, our optimization strategy determines the number of processors to be used in executing each nest based on the objective function and additional compilation constraints provided by the user. Our initial experience with this strategy shows that it is very successful in optimizing array-intensive applications on on-chip multiprocessors under energy and performance constraints.

Original languageEnglish (US)
Pages (from-to)703-708
Number of pages6
JournalProceedings-Design Automation Conference
DOIs
StatePublished - Jan 1 2002

Fingerprint

Linear programming
Computer systems
Energy utilization
Systems analysis

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering

Cite this

@article{8b9ceb3df17240f487a67cb20490565b,
title = "An integer linear programming based approach for parallelizing applications in on-chip multiprocessors",
abstract = "With energy consumption becoming one of the first-class optimization parameters in computer system design, compilation techniques that consider performance and energy simultaneously are expected to play a central role. In particular, compiling a given application code under performance and energy constraints is becoming an important problem. In this paper, we focus on an on-chip multiprocessor architecture and present a parallelization strategy based on integer linear programming. Given an array-intensive application, our optimization strategy determines the number of processors to be used in executing each nest based on the objective function and additional compilation constraints provided by the user. Our initial experience with this strategy shows that it is very successful in optimizing array-intensive applications on on-chip multiprocessors under energy and performance constraints.",
author = "I. Kadayif and Mahmut Kandemir and U. Sezer",
year = "2002",
month = "1",
day = "1",
doi = "10.1109/DAC.2002.1012715",
language = "English (US)",
pages = "703--708",
journal = "Proceedings - Design Automation Conference",
issn = "0738-100X",

}

TY - JOUR

T1 - An integer linear programming based approach for parallelizing applications in on-chip multiprocessors

AU - Kadayif, I.

AU - Kandemir, Mahmut

AU - Sezer, U.

PY - 2002/1/1

Y1 - 2002/1/1

N2 - With energy consumption becoming one of the first-class optimization parameters in computer system design, compilation techniques that consider performance and energy simultaneously are expected to play a central role. In particular, compiling a given application code under performance and energy constraints is becoming an important problem. In this paper, we focus on an on-chip multiprocessor architecture and present a parallelization strategy based on integer linear programming. Given an array-intensive application, our optimization strategy determines the number of processors to be used in executing each nest based on the objective function and additional compilation constraints provided by the user. Our initial experience with this strategy shows that it is very successful in optimizing array-intensive applications on on-chip multiprocessors under energy and performance constraints.

AB - With energy consumption becoming one of the first-class optimization parameters in computer system design, compilation techniques that consider performance and energy simultaneously are expected to play a central role. In particular, compiling a given application code under performance and energy constraints is becoming an important problem. In this paper, we focus on an on-chip multiprocessor architecture and present a parallelization strategy based on integer linear programming. Given an array-intensive application, our optimization strategy determines the number of processors to be used in executing each nest based on the objective function and additional compilation constraints provided by the user. Our initial experience with this strategy shows that it is very successful in optimizing array-intensive applications on on-chip multiprocessors under energy and performance constraints.

UR - http://www.scopus.com/inward/record.url?scp=0036045542&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0036045542&partnerID=8YFLogxK

U2 - 10.1109/DAC.2002.1012715

DO - 10.1109/DAC.2002.1012715

M3 - Article

SP - 703

EP - 708

JO - Proceedings - Design Automation Conference

JF - Proceedings - Design Automation Conference

SN - 0738-100X

ER -