An integrated optimization strategy for saving energy on multiprocessor-on-a-chip architectures

G. Chen, Mahmut Kandemir, I. Kolcu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In an on-chip multiprocessor, there exist two major ways of saving energy: voltage scaling and processor shut-down. This paper makes a case for an integrated strategy where these two techniques are applied in concert for the best energy savings. We present an integer linear programming (ILP) approach that selects the best combination of voltage scaling and processor shut-down.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International SOC Conference, SOCC 2003
EditorsDong S. Ha, Richard Auletta, John Chickanosky
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages253-254
Number of pages2
ISBN (Electronic)0780381823, 9780780381827
DOIs
StatePublished - Jan 1 2003
EventIEEE International SOC Conference, SOCC 2003 - Portland, United States
Duration: Sep 17 2003Sep 20 2003

Publication series

NameProceedings - IEEE International SOC Conference, SOCC 2003

Other

OtherIEEE International SOC Conference, SOCC 2003
CountryUnited States
CityPortland
Period9/17/039/20/03

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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    Chen, G., Kandemir, M., & Kolcu, I. (2003). An integrated optimization strategy for saving energy on multiprocessor-on-a-chip architectures. In D. S. Ha, R. Auletta, & J. Chickanosky (Eds.), Proceedings - IEEE International SOC Conference, SOCC 2003 (pp. 253-254). [1241507] (Proceedings - IEEE International SOC Conference, SOCC 2003). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SOC.2003.1241507