Abstract
In this paper, we describe an improved SPICE model for the negative capacitance field-effect transistor (NCFET). According to the law of conservation of charge, the model is built based on the relationship between the gate charge of the MOSFET and the charge reserved by the ferroelectric layer and includes the parasitic resistance and capacitance into consideration. Based on the model, the drain-induced barrier lowering (DIBL) and the negative resistance (NR) of the NCFET are analyzed. Finally, taking two well-known analog blocks (the current mirror and the latch comparator) for example, impacts of the DIBL effect and the NR property on analog circuit performances are discussed. Thanks to utilization of the NR feature, not only can impacts of the DIBL effect and the channel-length modulation (CLM) effect be alleviated to improve the mirroring accuracy, but also the comparison speed of the latch comparator be accelerated.
| Original language | English (US) |
|---|---|
| Article number | 8513804 |
| Pages (from-to) | 5525-5529 |
| Number of pages | 5 |
| Journal | IEEE Transactions on Electron Devices |
| Volume | 65 |
| Issue number | 12 |
| DOIs | |
| State | Published - Dec 1 2018 |
Fingerprint
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering
Cite this
}
Analysis of DIBL Effect and Negative Resistance Performance for NCFET Based on a Compact SPICE Model. / Liang, Yuhua; Li, Xueqing; Gupta, Sumeet Kumar; Datta, Suman; Narayanan, Vijaykrishnan.
In: IEEE Transactions on Electron Devices, Vol. 65, No. 12, 8513804, 01.12.2018, p. 5525-5529.Research output: Contribution to journal › Article
TY - JOUR
T1 - Analysis of DIBL Effect and Negative Resistance Performance for NCFET Based on a Compact SPICE Model
AU - Liang, Yuhua
AU - Li, Xueqing
AU - Gupta, Sumeet Kumar
AU - Datta, Suman
AU - Narayanan, Vijaykrishnan
PY - 2018/12/1
Y1 - 2018/12/1
N2 - In this paper, we describe an improved SPICE model for the negative capacitance field-effect transistor (NCFET). According to the law of conservation of charge, the model is built based on the relationship between the gate charge of the MOSFET and the charge reserved by the ferroelectric layer and includes the parasitic resistance and capacitance into consideration. Based on the model, the drain-induced barrier lowering (DIBL) and the negative resistance (NR) of the NCFET are analyzed. Finally, taking two well-known analog blocks (the current mirror and the latch comparator) for example, impacts of the DIBL effect and the NR property on analog circuit performances are discussed. Thanks to utilization of the NR feature, not only can impacts of the DIBL effect and the channel-length modulation (CLM) effect be alleviated to improve the mirroring accuracy, but also the comparison speed of the latch comparator be accelerated.
AB - In this paper, we describe an improved SPICE model for the negative capacitance field-effect transistor (NCFET). According to the law of conservation of charge, the model is built based on the relationship between the gate charge of the MOSFET and the charge reserved by the ferroelectric layer and includes the parasitic resistance and capacitance into consideration. Based on the model, the drain-induced barrier lowering (DIBL) and the negative resistance (NR) of the NCFET are analyzed. Finally, taking two well-known analog blocks (the current mirror and the latch comparator) for example, impacts of the DIBL effect and the NR property on analog circuit performances are discussed. Thanks to utilization of the NR feature, not only can impacts of the DIBL effect and the channel-length modulation (CLM) effect be alleviated to improve the mirroring accuracy, but also the comparison speed of the latch comparator be accelerated.
UR - http://www.scopus.com/inward/record.url?scp=85055710618&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85055710618&partnerID=8YFLogxK
U2 - 10.1109/TED.2018.2875661
DO - 10.1109/TED.2018.2875661
M3 - Article
AN - SCOPUS:85055710618
VL - 65
SP - 5525
EP - 5529
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
SN - 0018-9383
IS - 12
M1 - 8513804
ER -