Analysis of error recovery schemes for networks on chips

Srinivasan Murali, Theocharis Theocharides, Vijaykrishnan Narayanan, Mary Jane Irwin, Luca Benini, Giovanni De Micheli

Research output: Contribution to journalArticle

247 Citations (Scopus)

Abstract

Error resiliency is a must for NoCs, but it must not incur undue costs - particularly in terms of energy consumption. Here, the authors present and authoritative discussion of the trade-offs involved in various error recovery schemes, enabling designers to make optimal decisions.

Original languageEnglish (US)
Pages (from-to)434-442
Number of pages9
JournalIEEE Design and Test of Computers
Volume22
Issue number5
DOIs
StatePublished - Sep 1 2005

Fingerprint

Energy utilization
Costs
Network-on-chip

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Murali, S., Theocharides, T., Narayanan, V., Irwin, M. J., Benini, L., & De Micheli, G. (2005). Analysis of error recovery schemes for networks on chips. IEEE Design and Test of Computers, 22(5), 434-442. https://doi.org/10.1109/MDT.2005.104
Murali, Srinivasan ; Theocharides, Theocharis ; Narayanan, Vijaykrishnan ; Irwin, Mary Jane ; Benini, Luca ; De Micheli, Giovanni. / Analysis of error recovery schemes for networks on chips. In: IEEE Design and Test of Computers. 2005 ; Vol. 22, No. 5. pp. 434-442.
@article{483ae501d6d94e6a9dc58229a0118c2c,
title = "Analysis of error recovery schemes for networks on chips",
abstract = "Error resiliency is a must for NoCs, but it must not incur undue costs - particularly in terms of energy consumption. Here, the authors present and authoritative discussion of the trade-offs involved in various error recovery schemes, enabling designers to make optimal decisions.",
author = "Srinivasan Murali and Theocharis Theocharides and Vijaykrishnan Narayanan and Irwin, {Mary Jane} and Luca Benini and {De Micheli}, Giovanni",
year = "2005",
month = "9",
day = "1",
doi = "10.1109/MDT.2005.104",
language = "English (US)",
volume = "22",
pages = "434--442",
journal = "IEEE Design and Test",
issn = "2168-2356",
publisher = "IEEE Computer Society",
number = "5",

}

Murali, S, Theocharides, T, Narayanan, V, Irwin, MJ, Benini, L & De Micheli, G 2005, 'Analysis of error recovery schemes for networks on chips', IEEE Design and Test of Computers, vol. 22, no. 5, pp. 434-442. https://doi.org/10.1109/MDT.2005.104

Analysis of error recovery schemes for networks on chips. / Murali, Srinivasan; Theocharides, Theocharis; Narayanan, Vijaykrishnan; Irwin, Mary Jane; Benini, Luca; De Micheli, Giovanni.

In: IEEE Design and Test of Computers, Vol. 22, No. 5, 01.09.2005, p. 434-442.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Analysis of error recovery schemes for networks on chips

AU - Murali, Srinivasan

AU - Theocharides, Theocharis

AU - Narayanan, Vijaykrishnan

AU - Irwin, Mary Jane

AU - Benini, Luca

AU - De Micheli, Giovanni

PY - 2005/9/1

Y1 - 2005/9/1

N2 - Error resiliency is a must for NoCs, but it must not incur undue costs - particularly in terms of energy consumption. Here, the authors present and authoritative discussion of the trade-offs involved in various error recovery schemes, enabling designers to make optimal decisions.

AB - Error resiliency is a must for NoCs, but it must not incur undue costs - particularly in terms of energy consumption. Here, the authors present and authoritative discussion of the trade-offs involved in various error recovery schemes, enabling designers to make optimal decisions.

UR - http://www.scopus.com/inward/record.url?scp=27344448860&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=27344448860&partnerID=8YFLogxK

U2 - 10.1109/MDT.2005.104

DO - 10.1109/MDT.2005.104

M3 - Article

AN - SCOPUS:27344448860

VL - 22

SP - 434

EP - 442

JO - IEEE Design and Test

JF - IEEE Design and Test

SN - 2168-2356

IS - 5

ER -