Analysis of error recovery schemes for networks on chips

Srinivasan Murali, Theocharis Theocharides, N. Vijaykrishnan, Mary Jane Irwin, Luca Benini, Giovanni De Micheli

Research output: Contribution to journalArticle

252 Scopus citations

Abstract

Error resiliency is a must for NoCs, but it must not incur undue costs - particularly in terms of energy consumption. Here, the authors present and authoritative discussion of the trade-offs involved in various error recovery schemes, enabling designers to make optimal decisions.

Original languageEnglish (US)
Pages (from-to)434-442
Number of pages9
JournalIEEE Design and Test of Computers
Volume22
Issue number5
DOIs
StatePublished - Sep 1 2005

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All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Murali, S., Theocharides, T., Vijaykrishnan, N., Irwin, M. J., Benini, L., & De Micheli, G. (2005). Analysis of error recovery schemes for networks on chips. IEEE Design and Test of Computers, 22(5), 434-442. https://doi.org/10.1109/MDT.2005.104