Analysis of Row Hammer Attack on STTRAM

Mohammad Nasim Imtiaz Khan, Swaroop Ghosh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

In this paper, we model and investigate the impact of Row Hammering (RH) on Spin-Transfer Torque RAM (STTRAM) by exploiting its write operation. STTRAM suffers from high write current and long write latency which can result in ground bounce. The magnitude of the bounce depends on the old data and the new data that is being written. The bounce can propagate to the nearest word-line drivers and partially turn ON the access transistors making weak current flow through the memory bitcells and reducing their thermal energy barrier. Therefore, continuous write at a particular location can force the massive number of unselected bits to suffer from degraded thermal barrier due to weak RH current. Reduced thermal barrier may lead to retention failures and make the bits sensitive to stray magnetic field/thermal noise. Those bits can also suffer from read disturb if they are read. These issues could be even worse for Short Retention NVM (SRNVM) which is suitable for Last Level Cache (LLC) and has a base retention of only few seconds. The ground bounce can also propagate to bitline/ source-line drivers and the selected cells will experience lower headroom voltage. This will lead to read failure (due to degraded sense margin) and write failure (due to increased write latency). Simulation result indicates that RH attack can flip the bits in just 30.84secs for STTRAM with base retention of 1 min. In presence of elevated temperature, the retention time can be further reduced to 2.46secs and 0.19secs for T=50C and T=75C respectively. RH attack can increase read disturb by 2.09X for bitcell with 1min base retention at T=25C. Simulation result also indicates that RH attack can cause read/write failure if the bitcell being read/written experience 306mV (for data 0)/110mV (for writing 0-> 1) of bounce. To the best of our knowledge, this is the first RH attack study for STTRAM-based cache.

Original languageEnglish (US)
Title of host publicationProceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages75-82
Number of pages8
ISBN (Electronic)9781538684771
DOIs
StatePublished - Jan 16 2019
Event36th International Conference on Computer Design, ICCD 2018 - Orlando, United States
Duration: Oct 7 2018Oct 10 2018

Publication series

NameProceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018

Conference

Conference36th International Conference on Computer Design, ICCD 2018
CountryUnited States
CityOrlando
Period10/7/1810/10/18

Fingerprint

Hammers
Random access storage
Torque
Thermal noise
Energy barriers
Thermal energy
Transistors
Magnetic fields
Data storage equipment
Electric potential
Temperature
Hot Temperature

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Hardware and Architecture
  • Safety, Risk, Reliability and Quality

Cite this

Khan, M. N. I., & Ghosh, S. (2019). Analysis of Row Hammer Attack on STTRAM. In Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018 (pp. 75-82). [8615671] (Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICCD.2018.00021
Khan, Mohammad Nasim Imtiaz ; Ghosh, Swaroop. / Analysis of Row Hammer Attack on STTRAM. Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 75-82 (Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018).
@inproceedings{6d17646382c84049bda08cc1f76dfad6,
title = "Analysis of Row Hammer Attack on STTRAM",
abstract = "In this paper, we model and investigate the impact of Row Hammering (RH) on Spin-Transfer Torque RAM (STTRAM) by exploiting its write operation. STTRAM suffers from high write current and long write latency which can result in ground bounce. The magnitude of the bounce depends on the old data and the new data that is being written. The bounce can propagate to the nearest word-line drivers and partially turn ON the access transistors making weak current flow through the memory bitcells and reducing their thermal energy barrier. Therefore, continuous write at a particular location can force the massive number of unselected bits to suffer from degraded thermal barrier due to weak RH current. Reduced thermal barrier may lead to retention failures and make the bits sensitive to stray magnetic field/thermal noise. Those bits can also suffer from read disturb if they are read. These issues could be even worse for Short Retention NVM (SRNVM) which is suitable for Last Level Cache (LLC) and has a base retention of only few seconds. The ground bounce can also propagate to bitline/ source-line drivers and the selected cells will experience lower headroom voltage. This will lead to read failure (due to degraded sense margin) and write failure (due to increased write latency). Simulation result indicates that RH attack can flip the bits in just 30.84secs for STTRAM with base retention of 1 min. In presence of elevated temperature, the retention time can be further reduced to 2.46secs and 0.19secs for T=50C and T=75C respectively. RH attack can increase read disturb by 2.09X for bitcell with 1min base retention at T=25C. Simulation result also indicates that RH attack can cause read/write failure if the bitcell being read/written experience 306mV (for data 0)/110mV (for writing 0-> 1) of bounce. To the best of our knowledge, this is the first RH attack study for STTRAM-based cache.",
author = "Khan, {Mohammad Nasim Imtiaz} and Swaroop Ghosh",
year = "2019",
month = "1",
day = "16",
doi = "10.1109/ICCD.2018.00021",
language = "English (US)",
series = "Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "75--82",
booktitle = "Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018",
address = "United States",

}

Khan, MNI & Ghosh, S 2019, Analysis of Row Hammer Attack on STTRAM. in Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018., 8615671, Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018, Institute of Electrical and Electronics Engineers Inc., pp. 75-82, 36th International Conference on Computer Design, ICCD 2018, Orlando, United States, 10/7/18. https://doi.org/10.1109/ICCD.2018.00021

Analysis of Row Hammer Attack on STTRAM. / Khan, Mohammad Nasim Imtiaz; Ghosh, Swaroop.

Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018. Institute of Electrical and Electronics Engineers Inc., 2019. p. 75-82 8615671 (Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Analysis of Row Hammer Attack on STTRAM

AU - Khan, Mohammad Nasim Imtiaz

AU - Ghosh, Swaroop

PY - 2019/1/16

Y1 - 2019/1/16

N2 - In this paper, we model and investigate the impact of Row Hammering (RH) on Spin-Transfer Torque RAM (STTRAM) by exploiting its write operation. STTRAM suffers from high write current and long write latency which can result in ground bounce. The magnitude of the bounce depends on the old data and the new data that is being written. The bounce can propagate to the nearest word-line drivers and partially turn ON the access transistors making weak current flow through the memory bitcells and reducing their thermal energy barrier. Therefore, continuous write at a particular location can force the massive number of unselected bits to suffer from degraded thermal barrier due to weak RH current. Reduced thermal barrier may lead to retention failures and make the bits sensitive to stray magnetic field/thermal noise. Those bits can also suffer from read disturb if they are read. These issues could be even worse for Short Retention NVM (SRNVM) which is suitable for Last Level Cache (LLC) and has a base retention of only few seconds. The ground bounce can also propagate to bitline/ source-line drivers and the selected cells will experience lower headroom voltage. This will lead to read failure (due to degraded sense margin) and write failure (due to increased write latency). Simulation result indicates that RH attack can flip the bits in just 30.84secs for STTRAM with base retention of 1 min. In presence of elevated temperature, the retention time can be further reduced to 2.46secs and 0.19secs for T=50C and T=75C respectively. RH attack can increase read disturb by 2.09X for bitcell with 1min base retention at T=25C. Simulation result also indicates that RH attack can cause read/write failure if the bitcell being read/written experience 306mV (for data 0)/110mV (for writing 0-> 1) of bounce. To the best of our knowledge, this is the first RH attack study for STTRAM-based cache.

AB - In this paper, we model and investigate the impact of Row Hammering (RH) on Spin-Transfer Torque RAM (STTRAM) by exploiting its write operation. STTRAM suffers from high write current and long write latency which can result in ground bounce. The magnitude of the bounce depends on the old data and the new data that is being written. The bounce can propagate to the nearest word-line drivers and partially turn ON the access transistors making weak current flow through the memory bitcells and reducing their thermal energy barrier. Therefore, continuous write at a particular location can force the massive number of unselected bits to suffer from degraded thermal barrier due to weak RH current. Reduced thermal barrier may lead to retention failures and make the bits sensitive to stray magnetic field/thermal noise. Those bits can also suffer from read disturb if they are read. These issues could be even worse for Short Retention NVM (SRNVM) which is suitable for Last Level Cache (LLC) and has a base retention of only few seconds. The ground bounce can also propagate to bitline/ source-line drivers and the selected cells will experience lower headroom voltage. This will lead to read failure (due to degraded sense margin) and write failure (due to increased write latency). Simulation result indicates that RH attack can flip the bits in just 30.84secs for STTRAM with base retention of 1 min. In presence of elevated temperature, the retention time can be further reduced to 2.46secs and 0.19secs for T=50C and T=75C respectively. RH attack can increase read disturb by 2.09X for bitcell with 1min base retention at T=25C. Simulation result also indicates that RH attack can cause read/write failure if the bitcell being read/written experience 306mV (for data 0)/110mV (for writing 0-> 1) of bounce. To the best of our knowledge, this is the first RH attack study for STTRAM-based cache.

UR - http://www.scopus.com/inward/record.url?scp=85062226020&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85062226020&partnerID=8YFLogxK

U2 - 10.1109/ICCD.2018.00021

DO - 10.1109/ICCD.2018.00021

M3 - Conference contribution

AN - SCOPUS:85062226020

T3 - Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018

SP - 75

EP - 82

BT - Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

Khan MNI, Ghosh S. Analysis of Row Hammer Attack on STTRAM. In Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018. Institute of Electrical and Electronics Engineers Inc. 2019. p. 75-82. 8615671. (Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018). https://doi.org/10.1109/ICCD.2018.00021