Analysis of soft error rate in flip-flops and scannable latches

R. Ramanarayanan, V. Degalahal, N. Vijaykrishnan, M. J. Irwin, D. Duarte

Research output: Chapter in Book/Report/Conference proceedingConference contribution

36 Scopus citations

Abstract

Soft errors can be induced through radiation sources, with particles of low energy occurring far more frequently than particles of high energy. Therefore, smaller CMOS device are more easily affected by lower energy particles. Thus, soft errors are gaining importance as technology scales. Flip-flops, an important component of pipelined architectures, are becoming more susceptible to soft errors. This work analyzes soft error rates on a variety of flip-flops. The analysis was performed by implementing and simulating various designs in 70 nm, 1 V CMOS technology. First, we evaluate the critical charge for the susceptible nodes in each design. Further, we implement two hardening techniques and present the results. One attempts to increase the gate capacitance, the other improves the overall robustness of the circuit by replicating the master stage of the master-slave flip-flops, which leads to reduced power and area overhead.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International SOC Conference, SOCC 2003
EditorsDong S. Ha, Richard Auletta, John Chickanosky
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages231-234
Number of pages4
ISBN (Electronic)0780381823, 9780780381827
DOIs
StatePublished - 2003
EventIEEE International SOC Conference, SOCC 2003 - Portland, United States
Duration: Sep 17 2003Sep 20 2003

Publication series

NameProceedings - IEEE International SOC Conference, SOCC 2003

Other

OtherIEEE International SOC Conference, SOCC 2003
CountryUnited States
CityPortland
Period9/17/039/20/03

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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