Analyzing energy-delay behavior in room temperature single electron transistors

Vinay Saripalli, Vijaykrishnan Narayanan, Suman Datta

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

This paper presents Single Electron Transistor (SET) devices operating at room temperature as an attractive option to implement low energy consumption circuits with low-to-moderate performance requirements. Currently, such circuits are implemented using CMOS technologies operating at low supply voltages. CMOS is usually leakage dominated at such a low voltage regime and various optimizations are necessary to design low energy circuits. By discussing the energy-delay trade-offs for SET devices and comparing them to those of contemporary CMOS technology, we present an argument that SET devices may be more favorable compared to CMOS from the energy and delay standpoints at low supply voltages.

Original languageEnglish (US)
Title of host publicationVLSi Design 2010 - 23rd International Conference on VLSI Design, Held jointly with 9th International Conference on Embedded Systems
Pages399-404
Number of pages6
DOIs
StatePublished - 2010
Event23rd International Conference on VLSI Design, Held jointly with 9th International Conference on Embedded Systems, VLSi Design 2010 - Bangalore, India
Duration: Jan 3 2010Jan 7 2010

Other

Other23rd International Conference on VLSI Design, Held jointly with 9th International Conference on Embedded Systems, VLSi Design 2010
CountryIndia
CityBangalore
Period1/3/101/7/10

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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    Saripalli, V., Narayanan, V., & Datta, S. (2010). Analyzing energy-delay behavior in room temperature single electron transistors. In VLSi Design 2010 - 23rd International Conference on VLSI Design, Held jointly with 9th International Conference on Embedded Systems (pp. 399-404). [5401213] https://doi.org/10.1109/VLSI.Design.2010.48