Analyzing soft errors in leakage optimized SRAM design

V. Degalahal, N. Vijaykrishnan, M. J. Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

45 Citations (Scopus)

Abstract

Reducing leakage power and improving the reliability of data stored in the memory cells are both becoming challenging as technology scales down. While the smaller threshold voltages cause increased leakage, smaller supply voltages and node capacitances can be a problem for soft errors. This work compares the soft error rates of some recently proposed SRAM leakage optimization approaches. Our results using designs in 70nm technology show that many of these approaches may increase the soft error rates as compared to a standard 6T SRAM. Further, we demonstrate that there is a tradeoff between optimizing the leakage power and improving the immunity to soft error.

Original languageEnglish (US)
Title of host publicationProceedings - 16th International Conference on VLSI Design, VLSI 2003 - concurrently with the 2nd International Conference on Embedded Systems Design
PublisherIEEE Computer Society
Pages227-233
Number of pages7
ISBN (Electronic)0769518680
DOIs
StatePublished - Jan 1 2003
Event16th International Conference on VLSI Design, VLSI 2003 - concurrently with the 2nd International Conference on Embedded Systems Design - New Delhi, India
Duration: Jan 4 2003Jan 8 2003

Publication series

NameProceedings of the IEEE International Conference on VLSI Design
Volume2003-January
ISSN (Print)1063-9667

Other

Other16th International Conference on VLSI Design, VLSI 2003 - concurrently with the 2nd International Conference on Embedded Systems Design
CountryIndia
CityNew Delhi
Period1/4/031/8/03

Fingerprint

Static random access storage
Threshold voltage
Capacitance
Data storage equipment
Electric potential

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Degalahal, V., Vijaykrishnan, N., & Irwin, M. J. (2003). Analyzing soft errors in leakage optimized SRAM design. In Proceedings - 16th International Conference on VLSI Design, VLSI 2003 - concurrently with the 2nd International Conference on Embedded Systems Design (pp. 227-233). [1183141] (Proceedings of the IEEE International Conference on VLSI Design; Vol. 2003-January). IEEE Computer Society. https://doi.org/10.1109/ICVD.2003.1183141
Degalahal, V. ; Vijaykrishnan, N. ; Irwin, M. J. / Analyzing soft errors in leakage optimized SRAM design. Proceedings - 16th International Conference on VLSI Design, VLSI 2003 - concurrently with the 2nd International Conference on Embedded Systems Design. IEEE Computer Society, 2003. pp. 227-233 (Proceedings of the IEEE International Conference on VLSI Design).
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abstract = "Reducing leakage power and improving the reliability of data stored in the memory cells are both becoming challenging as technology scales down. While the smaller threshold voltages cause increased leakage, smaller supply voltages and node capacitances can be a problem for soft errors. This work compares the soft error rates of some recently proposed SRAM leakage optimization approaches. Our results using designs in 70nm technology show that many of these approaches may increase the soft error rates as compared to a standard 6T SRAM. Further, we demonstrate that there is a tradeoff between optimizing the leakage power and improving the immunity to soft error.",
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Degalahal, V, Vijaykrishnan, N & Irwin, MJ 2003, Analyzing soft errors in leakage optimized SRAM design. in Proceedings - 16th International Conference on VLSI Design, VLSI 2003 - concurrently with the 2nd International Conference on Embedded Systems Design., 1183141, Proceedings of the IEEE International Conference on VLSI Design, vol. 2003-January, IEEE Computer Society, pp. 227-233, 16th International Conference on VLSI Design, VLSI 2003 - concurrently with the 2nd International Conference on Embedded Systems Design, New Delhi, India, 1/4/03. https://doi.org/10.1109/ICVD.2003.1183141

Analyzing soft errors in leakage optimized SRAM design. / Degalahal, V.; Vijaykrishnan, N.; Irwin, M. J.

Proceedings - 16th International Conference on VLSI Design, VLSI 2003 - concurrently with the 2nd International Conference on Embedded Systems Design. IEEE Computer Society, 2003. p. 227-233 1183141 (Proceedings of the IEEE International Conference on VLSI Design; Vol. 2003-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Degalahal V, Vijaykrishnan N, Irwin MJ. Analyzing soft errors in leakage optimized SRAM design. In Proceedings - 16th International Conference on VLSI Design, VLSI 2003 - concurrently with the 2nd International Conference on Embedded Systems Design. IEEE Computer Society. 2003. p. 227-233. 1183141. (Proceedings of the IEEE International Conference on VLSI Design). https://doi.org/10.1109/ICVD.2003.1183141