Applications of advanced transmission electron microscopy techniques in gate stack scaling

Susanne Stemmer, James M. LeBeau, Joël Cagnon, Yoontae Hwang, Roman Engel-Herbert

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Advanced gate dielectric stacks are comprised of multiple layers of different materials, including high-k gate dielectrics, high-mobility semiconductor channels, metal gate electrodes and interfacial layers with sub-nanometer thickness. The composition, point defect chemistry, interface atomic structure and interaction between the layers determine the properties of novel gate stacks. This paper reviews recent applications of advanced transmission electron microscopy techniques to determine the atomic structure and defects in advanced gate stacks.

Original languageEnglish (US)
Title of host publication2009 Symposium on VLSI Technology, VLSIT 2009
Pages198-199
Number of pages2
StatePublished - 2009
Event2009 Symposium on VLSI Technology, VLSIT 2009 - Kyoto, Japan
Duration: Jun 16 2009Jun 18 2009

Other

Other2009 Symposium on VLSI Technology, VLSIT 2009
CountryJapan
CityKyoto
Period6/16/096/18/09

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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