Architecting microprocessor components in 3D design space

Balaji Vaidyanathan, Wei Lun Hung, Feng Wang, Yuan Xie, Vijaykrishnan Narayanan, Mary Jane Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

36 Scopus citations

Abstract

Interconnect is one of the major concerns in current and future microprocessor designs from both performance and power consumption perspective. The emergence of three-dimensional (3D) chip architectures, with its intrinsic capability to reduce the wire length, is one of the promising solutions to mitigate the interconnect related issues. In this paper we implement a few components of a microprocessor using custom design to show the potential performance and power benefits achievable through 3D integration under thermal constraints. We also introduce a standard cell based 3D design flow which leverages the commercial 2D design tools. Using this design flow we provide performance results of wide range of arithmetic units in 3D, thus introducing a fast method to analyze the performance benefits of 3D designs. In contrast to prior work, which mostly investigates single components of a processor, our work takes multiple components into consideration and the experimental results are promising in terms of delay and power reductions. Complex designs in 3D that have equivalent performance compared to a simple 2D designs is taken for IPC improvement analysis. An IPC improvement of 11% shown for a microprocessor implemented in 2-strata 3D technology.

Original languageEnglish (US)
Title of host publicationProceedings - 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems
Pages103-108
Number of pages6
DOIs
StatePublished - Dec 1 2007
Event20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems, VLSID'07 - Bangalore, India
Duration: Jan 6 2007Jan 10 2007

Publication series

NameProceedings of the IEEE International Conference on VLSI Design
ISSN (Print)1063-9667

Other

Other20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems, VLSID'07
CountryIndia
CityBangalore
Period1/6/071/10/07

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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    Vaidyanathan, B., Hung, W. L., Wang, F., Xie, Y., Narayanan, V., & Irwin, M. J. (2007). Architecting microprocessor components in 3D design space. In Proceedings - 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (pp. 103-108). [4092030] (Proceedings of the IEEE International Conference on VLSI Design). https://doi.org/10.1109/VLSID.2007.41