Architectural design for parallel fractal compression

K. P. Acken, H. N. Kim, M. J. Irwin, R. M. Owens

Research output: Contribution to conferencePaper

4 Scopus citations

Abstract

Fractal image compression has many features that makes it a powerful compression scheme, but it has been mainly restricted to archival storage due to its time consuming encoding algorithm. In this paper, we take a known quad-tree fractal encoding algorithm and design an ASIC parallel image processing array that can encode reasonably sized gray-scale images in real-time. In designing this architecture, we include novel optimizations that result in speed improvements at the algorithmic, architectural, and circuit levels.

Original languageEnglish (US)
Pages3-11
Number of pages9
StatePublished - Jan 1 1996
EventProceedings of the 1996 International Conference on Application-Specific Systems, Architectures and Processors - Chicago, IL, USA
Duration: Aug 19 1996Aug 21 1996

Other

OtherProceedings of the 1996 International Conference on Application-Specific Systems, Architectures and Processors
CityChicago, IL, USA
Period8/19/968/21/96

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Computer Networks and Communications

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    Acken, K. P., Kim, H. N., Irwin, M. J., & Owens, R. M. (1996). Architectural design for parallel fractal compression. 3-11. Paper presented at Proceedings of the 1996 International Conference on Application-Specific Systems, Architectures and Processors, Chicago, IL, USA, .