Architectural issues in Java runtime systems

R. Radhakrishnan, Vijaykrishnan Narayanan, L. K. John, Anand Sivasubramaniam

Research output: Contribution to conferencePaper

30 Scopus citations

Abstract

The Java Virtual Machine (JVM) is the corner stone of Java technology, and its efficiency in executing the portable Java bytecodes is crucial for the success of this technology. Interpretation, Just-In-Time (JIT) compilation, and hardware realization are well known solutions for a JVM, and previous research has proposed optimizations for each of these techniques. However, each technique has its pros and cons and may not be uniformly attractive for all hardware platforms. Instead, an understanding of the architectural implications of JVM implementations with real applications, can be crucial to the development of enabling technologies for efficient Java runtime system development on a wide range of platforms (from resource-rich servers to resource-constrained hand-held/embedded systems). Towards this goal, this paper examines architectural issues, from both the hardware and JVM implementation perspectives. It specifically explores the potential of a smart JIT compiler strategy that can dynamically interpret or compile based on associated costs, investigates the CPU and cache architectural support that would benefit JVM implementations, and examines the synchronization support for enhancing performance, using applications from the SpecJVM98 benchmarks.

Original languageEnglish (US)
Pages387-398
Number of pages12
StatePublished - Dec 1 2000
EventSixth International Symposium on High-Performance Computer Architecture - Toulouse, France
Duration: Jan 8 2000Jan 12 2000

Other

OtherSixth International Symposium on High-Performance Computer Architecture
CountryFrance
CityToulouse
Period1/8/001/12/00

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

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    Radhakrishnan, R., Narayanan, V., John, L. K., & Sivasubramaniam, A. (2000). Architectural issues in Java runtime systems. 387-398. Paper presented at Sixth International Symposium on High-Performance Computer Architecture, Toulouse, France.