Architectural optimizations for a floating point multiply-accumulate unit in a graphics pipeline

K. P. Acken, M. J. Irwin, R. M. Owens, A. K. Garga

Research output: Contribution to conferencePaperpeer-review

6 Scopus citations

Abstract

Scientific visualization and virtual reality have pushed three-dimensional graphics engines to their limits for updating scenes in real-time. One bottleneck of graphic systems is the transformation of an object's vertices into normalized space based on an evaluated transformation stack. This operation is often done in floating point, requiring a fast floating point multiply-accumulate unit. This paper presents architectural optimizations to a graphics pipeline floating point multiply-accumulate unit by using block floating point and parallelism to bypass or merge trivial operations in the matrix multiplications.

Original languageEnglish (US)
Pages65-71
Number of pages7
StatePublished - Jan 1 1996
EventProceedings of the 1996 International Conference on Application-Specific Systems, Architectures and Processors - Chicago, IL, USA
Duration: Aug 19 1996Aug 21 1996

Other

OtherProceedings of the 1996 International Conference on Application-Specific Systems, Architectures and Processors
CityChicago, IL, USA
Period8/19/968/21/96

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Computer Networks and Communications

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