Architectural optimizations for a floating point multiply-accumulate unit in a graphics pipeline

K. P. Acken, M. J. Irwin, R. M. Owens, A. K. Garga

Research output: Contribution to conferencePaper

6 Citations (Scopus)

Abstract

Scientific visualization and virtual reality have pushed three-dimensional graphics engines to their limits for updating scenes in real-time. One bottleneck of graphic systems is the transformation of an object's vertices into normalized space based on an evaluated transformation stack. This operation is often done in floating point, requiring a fast floating point multiply-accumulate unit. This paper presents architectural optimizations to a graphics pipeline floating point multiply-accumulate unit by using block floating point and parallelism to bypass or merge trivial operations in the matrix multiplications.

Original languageEnglish (US)
Pages65-71
Number of pages7
StatePublished - Jan 1 1996
EventProceedings of the 1996 International Conference on Application-Specific Systems, Architectures and Processors - Chicago, IL, USA
Duration: Aug 19 1996Aug 21 1996

Other

OtherProceedings of the 1996 International Conference on Application-Specific Systems, Architectures and Processors
CityChicago, IL, USA
Period8/19/968/21/96

Fingerprint

Data visualization
Virtual reality
Pipelines
Engines

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Computer Networks and Communications

Cite this

Acken, K. P., Irwin, M. J., Owens, R. M., & Garga, A. K. (1996). Architectural optimizations for a floating point multiply-accumulate unit in a graphics pipeline. 65-71. Paper presented at Proceedings of the 1996 International Conference on Application-Specific Systems, Architectures and Processors, Chicago, IL, USA, .
Acken, K. P. ; Irwin, M. J. ; Owens, R. M. ; Garga, A. K. / Architectural optimizations for a floating point multiply-accumulate unit in a graphics pipeline. Paper presented at Proceedings of the 1996 International Conference on Application-Specific Systems, Architectures and Processors, Chicago, IL, USA, .7 p.
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Acken, KP, Irwin, MJ, Owens, RM & Garga, AK 1996, 'Architectural optimizations for a floating point multiply-accumulate unit in a graphics pipeline', Paper presented at Proceedings of the 1996 International Conference on Application-Specific Systems, Architectures and Processors, Chicago, IL, USA, 8/19/96 - 8/21/96 pp. 65-71.

Architectural optimizations for a floating point multiply-accumulate unit in a graphics pipeline. / Acken, K. P.; Irwin, M. J.; Owens, R. M.; Garga, A. K.

1996. 65-71 Paper presented at Proceedings of the 1996 International Conference on Application-Specific Systems, Architectures and Processors, Chicago, IL, USA, .

Research output: Contribution to conferencePaper

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Acken KP, Irwin MJ, Owens RM, Garga AK. Architectural optimizations for a floating point multiply-accumulate unit in a graphics pipeline. 1996. Paper presented at Proceedings of the 1996 International Conference on Application-Specific Systems, Architectures and Processors, Chicago, IL, USA, .