Arithmetic unit design using 180nm TSV-based 3D stacking technology

J. Ouyang, G. Sun, Y. Chen, L. Duan, T. Zhang, Y. Xie, Mary Jane Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

21 Scopus citations

Abstract

We describe the design of two three dimensional arithmetic units (a 3D adder and a 3D multiplier) that are implemented using through-silicon-via 3D stacking technology. Compared to their 2D counterparts, our 3D adder incurs 10.6-34.3% less delay and 11.0-46.1% less energy when the width increases from 12-bit to 72-bit; the 32×32 3D multiplier incurs 14.4% less delay and 6.8% less energy, according to the post place and route results. The prototype chip including the implementations of a 3D adder, a 3D multiplier, and simple test interface has been delivered for fabrication in MIT Lincoln Laboratory, using their 3-tier SOI based 3D technology.

Original languageEnglish (US)
Title of host publication2009 IEEE International Conference on 3D System Integration, 3DIC 2009
DOIs
StatePublished - Dec 1 2009
Event2009 IEEE International Conference on 3D System Integration, 3DIC 2009 - San Francisco, CA, United States
Duration: Sep 28 2009Sep 30 2009

Publication series

Name2009 IEEE International Conference on 3D System Integration, 3DIC 2009

Other

Other2009 IEEE International Conference on 3D System Integration, 3DIC 2009
CountryUnited States
CitySan Francisco, CA
Period9/28/099/30/09

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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