TY - JOUR
T1 - Asymmetric drain spacer extension (ADSE) FinFETs for low-power and robust SRAMs
AU - Goel, Ashish
AU - Gupta, Sumeet Kumar
AU - Roy, Kaushik
N1 - Funding Information:
Manuscript received March 3, 2010; revised August 18, 2010; accepted October 20, 2010. Date of publication November 29, 2010; date of current version January 21, 2011. This work was supported in part by the Focused Center Research Program under C2S2 and through an Intel Ph.D. fellowship. The review of this paper was arranged by Editor J. Woo.
PY - 2011/2
Y1 - 2011/2
N2 - In this paper, we analyze and optimize FinFETs with asymmetric drain spacer extension (ADSE) that introduces a gate underlap only on the drain side. We present a physics-based discussion of currentvoltage relationships, short channel effects, and leakage and show the application of ADSE FinFETs in 6T static random access memory (SRAM) bit cell. By exploiting asymmetry in current, we show that it is possible to achieve improvement in both read and write stability for the 6T SRAM bit cell, along with reduction in cell leakage at the cost of negligible increase in access time and area. We also propose a general circuit-aware device optimization methodology for SRAM design. We use this methodology to optimize the underlap in ADSE FinFETs. Compared to conventional FinFETs, we achieve 57% reduction in leakage, 11% improvement in read static-noise margin, and 6% improvement in write margin, with 7% increase in access time and cell area.
AB - In this paper, we analyze and optimize FinFETs with asymmetric drain spacer extension (ADSE) that introduces a gate underlap only on the drain side. We present a physics-based discussion of currentvoltage relationships, short channel effects, and leakage and show the application of ADSE FinFETs in 6T static random access memory (SRAM) bit cell. By exploiting asymmetry in current, we show that it is possible to achieve improvement in both read and write stability for the 6T SRAM bit cell, along with reduction in cell leakage at the cost of negligible increase in access time and area. We also propose a general circuit-aware device optimization methodology for SRAM design. We use this methodology to optimize the underlap in ADSE FinFETs. Compared to conventional FinFETs, we achieve 57% reduction in leakage, 11% improvement in read static-noise margin, and 6% improvement in write margin, with 7% increase in access time and cell area.
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U2 - 10.1109/TED.2010.2090421
DO - 10.1109/TED.2010.2090421
M3 - Article
AN - SCOPUS:79151478067
VL - 58
SP - 296
EP - 308
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
SN - 0018-9383
IS - 2
M1 - 5643924
ER -