Automatic feedback control of shared hybrid caches in 3D chip multiprocessors

Akbar Sharifi, Mahmut Kandemir

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

3D integration enables building caches from different types of technologies such as SRAM, Magnetic RAM (MRAM), DRAM, and Phase-change RAM (PRAM). Hybrid cache architectures (HCAs) have been proposed to take advantage of the benefits offered by these types of technologies. Employing this novel cache architecture to build shared caches in chip multiprocessors (CMPs) can lead to significant performance and power consumption improvements. In this paper, we focus on a 3D CMP design in which the shared last level L2 cache is composed of an MRAM layer and an SRAM layer stacked upon the processing cores and present a control theory centric approach designed to partition this shared hybrid L2 cache space dynamically among concurrently running applications in order to satisfy the application-level performance QoS targets. At each time interval, the two layers of the hybrid L2 cache are partitioned, based on the cache demands made by the controllers of the applications, to satisfy the specified performance targets. We evaluate our feedback control based scheme using various workloads. Our experimental evaluation shows that the proposed scheme is able to satisfy the specified performance QoS in most of the tested cases, by partitioning the hybrid cache space of the 3D CMP among co-runner applications.

Original languageEnglish (US)
Title of host publicationProceedings - 19th International Euromicro Conference on Parallel, Distributed, and Network-Based Processing, PDP 2011
Pages393-400
Number of pages8
DOIs
StatePublished - Apr 26 2011
Event19th International Euromicro Conference on Parallel, Distributed, and Network-Based Processing, PDP 2011 - Ayia Napa, Cyprus
Duration: Feb 9 2011Feb 11 2011

Publication series

NameProceedings - 19th International Euromicro Conference on Parallel, Distributed, and Network-Based Processing, PDP 2011

Other

Other19th International Euromicro Conference on Parallel, Distributed, and Network-Based Processing, PDP 2011
CountryCyprus
CityAyia Napa
Period2/9/112/11/11

Fingerprint

Feedback control
Random access storage
Static random access storage
Quality of service
Dynamic random access storage
Control theory
Electric power utilization
Controllers
Processing

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Information Systems
  • Software

Cite this

Sharifi, A., & Kandemir, M. (2011). Automatic feedback control of shared hybrid caches in 3D chip multiprocessors. In Proceedings - 19th International Euromicro Conference on Parallel, Distributed, and Network-Based Processing, PDP 2011 (pp. 393-400). [5739025] (Proceedings - 19th International Euromicro Conference on Parallel, Distributed, and Network-Based Processing, PDP 2011). https://doi.org/10.1109/PDP.2011.83
Sharifi, Akbar ; Kandemir, Mahmut. / Automatic feedback control of shared hybrid caches in 3D chip multiprocessors. Proceedings - 19th International Euromicro Conference on Parallel, Distributed, and Network-Based Processing, PDP 2011. 2011. pp. 393-400 (Proceedings - 19th International Euromicro Conference on Parallel, Distributed, and Network-Based Processing, PDP 2011).
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abstract = "3D integration enables building caches from different types of technologies such as SRAM, Magnetic RAM (MRAM), DRAM, and Phase-change RAM (PRAM). Hybrid cache architectures (HCAs) have been proposed to take advantage of the benefits offered by these types of technologies. Employing this novel cache architecture to build shared caches in chip multiprocessors (CMPs) can lead to significant performance and power consumption improvements. In this paper, we focus on a 3D CMP design in which the shared last level L2 cache is composed of an MRAM layer and an SRAM layer stacked upon the processing cores and present a control theory centric approach designed to partition this shared hybrid L2 cache space dynamically among concurrently running applications in order to satisfy the application-level performance QoS targets. At each time interval, the two layers of the hybrid L2 cache are partitioned, based on the cache demands made by the controllers of the applications, to satisfy the specified performance targets. We evaluate our feedback control based scheme using various workloads. Our experimental evaluation shows that the proposed scheme is able to satisfy the specified performance QoS in most of the tested cases, by partitioning the hybrid cache space of the 3D CMP among co-runner applications.",
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Sharifi, A & Kandemir, M 2011, Automatic feedback control of shared hybrid caches in 3D chip multiprocessors. in Proceedings - 19th International Euromicro Conference on Parallel, Distributed, and Network-Based Processing, PDP 2011., 5739025, Proceedings - 19th International Euromicro Conference on Parallel, Distributed, and Network-Based Processing, PDP 2011, pp. 393-400, 19th International Euromicro Conference on Parallel, Distributed, and Network-Based Processing, PDP 2011, Ayia Napa, Cyprus, 2/9/11. https://doi.org/10.1109/PDP.2011.83

Automatic feedback control of shared hybrid caches in 3D chip multiprocessors. / Sharifi, Akbar; Kandemir, Mahmut.

Proceedings - 19th International Euromicro Conference on Parallel, Distributed, and Network-Based Processing, PDP 2011. 2011. p. 393-400 5739025 (Proceedings - 19th International Euromicro Conference on Parallel, Distributed, and Network-Based Processing, PDP 2011).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Sharifi A, Kandemir M. Automatic feedback control of shared hybrid caches in 3D chip multiprocessors. In Proceedings - 19th International Euromicro Conference on Parallel, Distributed, and Network-Based Processing, PDP 2011. 2011. p. 393-400. 5739025. (Proceedings - 19th International Euromicro Conference on Parallel, Distributed, and Network-Based Processing, PDP 2011). https://doi.org/10.1109/PDP.2011.83