Bandwidth Availability of Multiple-Bus Multiprocessors

Chita R. Das, Laxmi N. Bhuyan

Research output: Contribution to journalArticlepeer-review

62 Scopus citations

Abstract

Multiprocessor systems should be designed considering both performance and reliability issues. They should support graceful degradation by isolating the failed components and by reconfiguring to a new state with decreased performance. We present in this paper the effect of failures on the performance of multiple-bus multiprocessors. Bandwidth expressions for this architecture are derived for uniform and nonuniform memory references. Mathematical models are developed to compute the reliability and the performance related bandwidth availability (BA). The results obtained for the multiple-bus interconnection are compared with those of a crossbar. The models are also extended to analyze the partial bus structure where the memories are divided into groups and each group is connected to a subset of buses. The reliability and the BA of the multiple-bus and partial-buses architectures are compared.

Original languageEnglish (US)
Pages (from-to)918-926
Number of pages9
JournalIEEE Transactions on Computers
VolumeC-34
Issue number10
DOIs
StatePublished - Oct 1985

All Science Journal Classification (ASJC) codes

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics

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