Banked scratch-pad memory management for reducing leakage energy consumption

M. Kandemir, M. J. Irwin, G. Chen, I. Kolcu

Research output: Contribution to journalConference article

20 Citations (Scopus)

Abstract

Current trends indicate that leakage energy consumption will be an important concern in upcoming process technologies. In this paper, we propose a compiler-based leakage energy optimization strategy for on-chip scratch-pad memories (SPMs). The idea is to divide SPM into banks and use compiler-guided data layout optimization and data migration to maximize SPM bank idleness, thereby increasing the chances of placing banks into low-power (low-leakage) state.

Original languageEnglish (US)
Pages (from-to)120-124
Number of pages5
JournalIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
StatePublished - Dec 1 2004
EventICCAD-2004 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers - San Jose, CA, United States
Duration: Nov 7 2004Nov 11 2004

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Energy utilization
Data storage equipment

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

Cite this

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Banked scratch-pad memory management for reducing leakage energy consumption. / Kandemir, M.; Irwin, M. J.; Chen, G.; Kolcu, I.

In: IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, 01.12.2004, p. 120-124.

Research output: Contribution to journalConference article

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AU - Irwin, M. J.

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AU - Kolcu, I.

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