It is the thesis of this paper that from an implementation point of view it is often the case that the chip area occupied by a VLSI signal processor is dominated and, therefore, largely determined by the area that must be devoted to multipliers. Therefore, signal processors that have high multiplier utilization (i.e., attain a higher throughput for a given number of multipliers) are of interest because it is possible for them to also attain good VLSI area utilization. We present several signal processing architectures that have optimal multiplier utilization. We compare these architectures to several more conventional alternatives. We also demonstrate how our architectures achieve better multiplier utilization and, hence, VLSI area utilization without suffering a degradation in utilization of other resources (e.g., adders and interconnect).
All Science Journal Classification (ASJC) codes
- Theoretical Computer Science
- Hardware and Architecture
- Computational Theory and Mathematics