Buffer design for wide-area ATM networks using virtual finishing times

Research output: Contribution to conferencePaper

Abstract

This paper is concerned with the design of a class of priority buffering strategies suitable for public, wide-area ATM networks. We specify design goals for such strategies including ease of implementation and the ability to guarantee minimum bandwidths to individual buffers. Packetized generalized processor sharing is briefly discussed and a minimum-bandwidth result for self-clocked fair queueing is given. We revisit an approach originally proposed by L. Zhang and prove that it is appropriate for ATM. Some novel, related approaches are described and analyzed.

Original languageEnglish (US)
Pages1901-1905
Number of pages5
StatePublished - Jan 1 1995
EventProceedings of the 1995 IEEE International Conference on Communications. Part 1 (of 3) - Seattle, WA, USA
Duration: Jun 18 1995Jun 22 1995

Other

OtherProceedings of the 1995 IEEE International Conference on Communications. Part 1 (of 3)
CitySeattle, WA, USA
Period6/18/956/22/95

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

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  • Cite this

    Hung, A., & Kesidis, G. (1995). Buffer design for wide-area ATM networks using virtual finishing times. 1901-1905. Paper presented at Proceedings of the 1995 IEEE International Conference on Communications. Part 1 (of 3), Seattle, WA, USA, .