Cache revive: Architecting volatile STT-RAM caches for enhanced performance in CMPs

Adwait Jog, Asit K. Mishra, Cong Xu, Yuan Xie, Vijaykrishnan Narayanan, Ravishankar Iyer, Chita R. Das

Research output: Chapter in Book/Report/Conference proceedingConference contribution

143 Citations (Scopus)

Abstract

High density, low leakage and non-volatility are the attractive features of Spin-Transfer-Torque-RAM (STT-RAM), which has made it a strong competitor against SRAM as a universal memory replacement in multi-core systems. However, STT-RAM suffers from high write latency and energy which has impeded its widespread adoption. To this end, we look at trading-off STT-RAM's non-volatility property (data-retention-time) to overcome these problems. We formulate the relationship between retention-time and write-latency, and find optimal retention-time for architecting an efficient cache hierarchy using STT-RAM. Our results show that, compared to SRAM-based design, our proposal can improve performance and energy consumption by 18% and 60%, respectively.

Original languageEnglish (US)
Title of host publicationProceedings of the 49th Annual Design Automation Conference, DAC '12
Pages243-252
Number of pages10
DOIs
StatePublished - Jul 11 2012
Event49th Annual Design Automation Conference, DAC '12 - San Francisco, CA, United States
Duration: Jun 3 2012Jun 7 2012

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X

Other

Other49th Annual Design Automation Conference, DAC '12
CountryUnited States
CitySan Francisco, CA
Period6/3/126/7/12

Fingerprint

Volatiles
Random access storage
Cache
Torque
Latency
Static random access storage
Leakage
Energy Consumption
Replacement
Energy utilization
Energy
Data storage equipment

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modeling and Simulation

Cite this

Jog, A., Mishra, A. K., Xu, C., Xie, Y., Narayanan, V., Iyer, R., & Das, C. R. (2012). Cache revive: Architecting volatile STT-RAM caches for enhanced performance in CMPs. In Proceedings of the 49th Annual Design Automation Conference, DAC '12 (pp. 243-252). (Proceedings - Design Automation Conference). https://doi.org/10.1145/2228360.2228406
Jog, Adwait ; Mishra, Asit K. ; Xu, Cong ; Xie, Yuan ; Narayanan, Vijaykrishnan ; Iyer, Ravishankar ; Das, Chita R. / Cache revive : Architecting volatile STT-RAM caches for enhanced performance in CMPs. Proceedings of the 49th Annual Design Automation Conference, DAC '12. 2012. pp. 243-252 (Proceedings - Design Automation Conference).
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Jog, A, Mishra, AK, Xu, C, Xie, Y, Narayanan, V, Iyer, R & Das, CR 2012, Cache revive: Architecting volatile STT-RAM caches for enhanced performance in CMPs. in Proceedings of the 49th Annual Design Automation Conference, DAC '12. Proceedings - Design Automation Conference, pp. 243-252, 49th Annual Design Automation Conference, DAC '12, San Francisco, CA, United States, 6/3/12. https://doi.org/10.1145/2228360.2228406

Cache revive : Architecting volatile STT-RAM caches for enhanced performance in CMPs. / Jog, Adwait; Mishra, Asit K.; Xu, Cong; Xie, Yuan; Narayanan, Vijaykrishnan; Iyer, Ravishankar; Das, Chita R.

Proceedings of the 49th Annual Design Automation Conference, DAC '12. 2012. p. 243-252 (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Jog A, Mishra AK, Xu C, Xie Y, Narayanan V, Iyer R et al. Cache revive: Architecting volatile STT-RAM caches for enhanced performance in CMPs. In Proceedings of the 49th Annual Design Automation Conference, DAC '12. 2012. p. 243-252. (Proceedings - Design Automation Conference). https://doi.org/10.1145/2228360.2228406