Abstract
High density, low leakage and non-volatility are the attractive features of Spin-Transfer-Torque-RAM (STT-RAM), which has made it a strong competitor against SRAM as a universal memory replacement in multi-core systems. However, STT-RAM suffers from high write latency and energy which has impeded its widespread adoption. To this end, we look at trading-off STT-RAM's non-volatility property (data-retention-time) to overcome these problems. We formulate the relationship between retention-time and write-latency, and find optimal retention-time for architecting an efficient cache hierarchy using STT-RAM. Our results show that, compared to SRAM-based design, our proposal can improve performance and energy consumption by 18% and 60%, respectively.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings of the 49th Annual Design Automation Conference, DAC '12 |
| Pages | 243-252 |
| Number of pages | 10 |
| DOIs | |
| State | Published - Jul 11 2012 |
| Event | 49th Annual Design Automation Conference, DAC '12 - San Francisco, CA, United States Duration: Jun 3 2012 → Jun 7 2012 |
Publication series
| Name | Proceedings - Design Automation Conference |
|---|---|
| ISSN (Print) | 0738-100X |
Other
| Other | 49th Annual Design Automation Conference, DAC '12 |
|---|---|
| Country | United States |
| City | San Francisco, CA |
| Period | 6/3/12 → 6/7/12 |
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All Science Journal Classification (ASJC) codes
- Computer Science Applications
- Control and Systems Engineering
- Electrical and Electronic Engineering
- Modeling and Simulation
Cite this
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Cache revive : Architecting volatile STT-RAM caches for enhanced performance in CMPs. / Jog, Adwait; Mishra, Asit K.; Xu, Cong; Xie, Yuan; Narayanan, Vijaykrishnan; Iyer, Ravishankar; Das, Chita R.
Proceedings of the 49th Annual Design Automation Conference, DAC '12. 2012. p. 243-252 (Proceedings - Design Automation Conference).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Cache revive
T2 - Architecting volatile STT-RAM caches for enhanced performance in CMPs
AU - Jog, Adwait
AU - Mishra, Asit K.
AU - Xu, Cong
AU - Xie, Yuan
AU - Narayanan, Vijaykrishnan
AU - Iyer, Ravishankar
AU - Das, Chita R.
PY - 2012/7/11
Y1 - 2012/7/11
N2 - High density, low leakage and non-volatility are the attractive features of Spin-Transfer-Torque-RAM (STT-RAM), which has made it a strong competitor against SRAM as a universal memory replacement in multi-core systems. However, STT-RAM suffers from high write latency and energy which has impeded its widespread adoption. To this end, we look at trading-off STT-RAM's non-volatility property (data-retention-time) to overcome these problems. We formulate the relationship between retention-time and write-latency, and find optimal retention-time for architecting an efficient cache hierarchy using STT-RAM. Our results show that, compared to SRAM-based design, our proposal can improve performance and energy consumption by 18% and 60%, respectively.
AB - High density, low leakage and non-volatility are the attractive features of Spin-Transfer-Torque-RAM (STT-RAM), which has made it a strong competitor against SRAM as a universal memory replacement in multi-core systems. However, STT-RAM suffers from high write latency and energy which has impeded its widespread adoption. To this end, we look at trading-off STT-RAM's non-volatility property (data-retention-time) to overcome these problems. We formulate the relationship between retention-time and write-latency, and find optimal retention-time for architecting an efficient cache hierarchy using STT-RAM. Our results show that, compared to SRAM-based design, our proposal can improve performance and energy consumption by 18% and 60%, respectively.
UR - http://www.scopus.com/inward/record.url?scp=84863554441&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84863554441&partnerID=8YFLogxK
U2 - 10.1145/2228360.2228406
DO - 10.1145/2228360.2228406
M3 - Conference contribution
AN - SCOPUS:84863554441
SN - 9781450311991
T3 - Proceedings - Design Automation Conference
SP - 243
EP - 252
BT - Proceedings of the 49th Annual Design Automation Conference, DAC '12
ER -