Cache revive: Architecting volatile STT-RAM caches for enhanced performance in CMPs

Adwait Jog, Asit K. Mishra, Cong Xu, Yuan Xie, Vijaykrishnan Narayanan, Ravishankar Iyer, Chita R. Das

Research output: Chapter in Book/Report/Conference proceedingConference contribution

178 Scopus citations

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Mathematics

Engineering & Materials Science