Cache topology aware computation mapping for multicores

Mahmut Kandemir, Taylan Yemliha, Saiprashanth Muralidhara, Shekhar Srikantaiah, Mary Jane Irwin, Yuanrui Zhang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Scopus citations

Abstract

The main contribution of this paper is a compiler based, cache topology aware code optimization scheme for emerging multicore systems. This scheme distributes the iterations of a loop to be executed in parallel across the cores of a target multicore machine and schedules the iterations assigned to each core. Our goal is to improve the utilization of the on-chip multi-layer cache hierarchy and to maximize overall application performance. We evaluate our cache topology aware approach using a set of twelve applications and three different commercial multicore machines. In addition, to study some of our experimental parameters in detail and to explore future multicore machines (with higher core counts and deeper on-chip cache hierarchies), we also conduct a simulation based study. The results collected from our experiments with three Intel multicore machines show that the proposed compiler-based approach is very effective in enhancing performance. In addition, our simulation results indicate that optimizing for the on-chip cache hierarchy will be even more important in future multicores with increasing numbers of cores and cache levels.

Original languageEnglish (US)
Title of host publicationPLDI'10 - Proceedings of the 2010 ACM SIGPLAN Conference on Programming Language Design and Implementation
Pages74-85
Number of pages12
DOIs
StatePublished - Jul 23 2010
EventACM SIGPLAN 2010 Conference on Programming Language Design and Implementation, PLDI 2010 - Toronto, ON, Canada
Duration: Jun 5 2010Jun 10 2010

Publication series

NameProceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI)

Other

OtherACM SIGPLAN 2010 Conference on Programming Language Design and Implementation, PLDI 2010
CountryCanada
CityToronto, ON
Period6/5/106/10/10

All Science Journal Classification (ASJC) codes

  • Software

Fingerprint Dive into the research topics of 'Cache topology aware computation mapping for multicores'. Together they form a unique fingerprint.

Cite this